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| never stop thinking. falc ? 56 e1/t1/j1 framer and line interface component for long- and short-haul applications pef 2256 h/e, version 2.1 hardware description user?s manual, ds1.1, oct. 2003 wired communications
abm ? , ace ? , aop ? , arcofi ? , asm ? , asp ? , digitape ? , duslic ? , epic ? , elic ? , falc ? , geminax ? , idec ? , inca ? , iom ? , ipat ? -2, isac ? , itac ? , iwe ? , iworx ? , musac ? , muslic ? , octat ? , optiport ? , potswire ? , quat ? , quadfalc ? , scout ? , sicat ? , sicofi ? , sidec ? , slicofi ? , smint ? , socrates ? , vinetic ? , 10basev ? , 10basevx ? are registered trademarks of infineon technologies ag. 10bases?, easyport?, vdslite? are trademarks of infineon technologies ag. microsoft ? is a registered trademark of microsoft corporation, linux ? of linus torvalds, visio ? of visio corporation, and framemaker ? of adobe systems incorporated. the information in this document is subject to change without notice. edition 2003-10-23 published by infineon technologies ag, st.-martin-strasse 53, 81669 mnchen, germany ? infineon technologies ag 2003. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. pef 2256 h/e revision history: 2003-10-23 ds1.1 previous version: ./. page subjects (major changes since last revision) falc ? 56 pef 2256 h/e table of contents page user?s manual 3 ds1.1, 2003-10-23 hardware description preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.2 typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2 external signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.1 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.2 pin diagram p-mqfp-80-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.3 pin diagram p-lbga-81-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.4 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.4.1 input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3 functional description e1/t1/j1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.1 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.3 functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.3.1 microprocessor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.3.1.1 mixed byte/word access to the fifos . . . . . . . . . . . . . . . . . . . . . . . 51 3.3.1.2 fifo structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.3.1.3 interrupt interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.3.2 boundary scan interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 3.3.3 master clocking unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.4 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.4.1 power supply configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.4.2 power supply de-coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4 functional description e1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.1 receive path in e1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.1.1 receive line interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.1.2 receive short and long-haul interface . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.1.3 receive equalization network (e1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.1.4 receive line attenuation indication (e1) . . . . . . . . . . . . . . . . . . . . . . . . 64 4.1.5 receive clock and data recovery (e1) . . . . . . . . . . . . . . . . . . . . . . . . 64 4.1.6 receive line coding (e1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.1.7 receive line termination (e1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.1.8 receive line monitoring mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.1.9 loss-of-signal detection (e1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4.1.10 receive jitter attenuator (e1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.1.11 jitter tolerance (e1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 4.1.12 output jitter (e1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 4.1.13 framer/synchronizer (e1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4.1.14 receive elastic buffer (e1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4.1.15 receive signaling controller (e1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 falc ? 56 pef 2256 h/e table of contents page user?s manual 4 ds1.1, 2003-10-23 hardware description 4.1.15.1 hdlc or lapd access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 4.1.15.2 support of signaling system #7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 4.1.15.3 sa-bit access (e1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 4.1.15.4 channel associated signaling cas (e1, serial mode) . . . . . . . . . . . 80 4.1.15.5 channel associated signaling cas (e1, p access mode) . . . . . . . 81 4.2 framer operating modes (e1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 4.2.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 4.2.2 doubleframe format (e1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 4.2.2.1 transmit transparent modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 4.2.2.2 synchronization procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 4.2.2.3 a-bit access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 4.2.2.4 sa-bit access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 4.2.3 crc-multiframe (e1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 4.2.3.1 synchronization procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 4.2.3.2 automatic force resynchronization (e1) . . . . . . . . . . . . . . . . . . . . . 88 4.2.3.3 floating multiframe alignment window (e1) . . . . . . . . . . . . . . . . . . . 88 4.2.3.4 crc4 performance monitoring (e1) . . . . . . . . . . . . . . . . . . . . . . . . . 88 4.2.3.5 modified crc4 multiframe alignment algorithm (e1) . . . . . . . . . . . . 88 4.2.3.6 a-bit access (e1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 4.2.3.7 sa-bit access (e1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 4.2.3.8 e-bit access (e1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 4.3 additional receive framer functions (e1) . . . . . . . . . . . . . . . . . . . . . . . . 93 4.3.1 error performance monitoring and alarm handling . . . . . . . . . . . . . . . . 93 4.3.2 auto modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 4.3.2.1 automatic remote alarm access . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 4.3.2.2 automatic e-bit access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 4.3.2.3 automatic ais to system interface . . . . . . . . . . . . . . . . . . . . . . . . . . 94 4.3.2.4 automatic clock source switching . . . . . . . . . . . . . . . . . . . . . . . . . . 95 4.3.2.5 automatic freeze signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 4.3.3 error counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 4.3.4 errored second . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 4.3.5 one-second timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 4.3.6 in-band loop generation and detection . . . . . . . . . . . . . . . . . . . . . . . . 96 4.3.7 time slot 0 transparent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 4.4 transmit path in e1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 4.4.1 transmitter (e1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 4.4.2 transmit line interface (e1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 4.4.3 transmit jitter attenuator (e1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 4.4.4 transmit elastic buffer (e1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 4.4.5 programmable pulse shaper (e1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 4.4.6 transmit line monitor (e1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 4.4.7 transmit signaling controller (e1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 falc ? 56 pef 2256 h/e table of contents page user?s manual 5 ds1.1, 2003-10-23 hardware description 4.4.7.1 hdlc or lapd access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 4.4.7.2 support of signaling system #7 . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 4.4.7.3 sa-bit access (e1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 4.4.7.4 channel associated signaling cas (e1, serial mode) . . . . . . . . . . 104 4.4.7.5 channel associated signaling cas (e1, p access mode) . . . . . . 104 4.5 system interface in e1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 4.5.1 receive system interface (e1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 4.5.1.1 receive offset programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 4.5.2 transmit system interface (e1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 4.5.2.1 transmit offset programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 4.5.3 time slot assigner (e1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 4.6 test functions (e1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 4.6.1 pseudo-random binary sequence generation and monitor . . . . . . . . 117 4.6.2 remote loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 4.6.3 payload loop-back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 4.6.4 local loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 4.6.5 single channel loop-back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 4.6.6 alarm simulation (e1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 4.6.7 single bit defect insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 5 functional description t1/j1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 5.1 receive path in t1/j1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 5.1.1 receive line interface (t1/j1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 5.1.2 receive short and long-haul interface (t1/j1) . . . . . . . . . . . . . . . . . 122 5.1.3 receive equalization network (t1/j1) . . . . . . . . . . . . . . . . . . . . . . . . . 123 5.1.4 receive line attenuation indication (t1/j1) . . . . . . . . . . . . . . . . . . . . 123 5.1.5 receive clock and data recovery (t1/j1) . . . . . . . . . . . . . . . . . . . . . 123 5.1.6 receive line coding (t1/j1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 5.1.7 receive line termination (t1/j1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 5.1.8 receive line monitoring mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 5.1.9 loss-of-signal detection (t1/j1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 5.1.10 receive jitter attenuator (t1/j1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 5.1.11 jitter tolerance (t1/j1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 5.1.12 output jitter (t1/j1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 5.1.13 framer/synchronizer (t1/j1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 5.1.14 receive elastic buffer (t1/j1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 5.1.15 receive signaling controller (t1/j1) . . . . . . . . . . . . . . . . . . . . . . . . . . 138 5.1.15.1 hdlc or lapd access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 5.1.15.2 support of signaling system #7 . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 5.1.15.3 cas bit-robbing (t1/j1, serial mode) . . . . . . . . . . . . . . . . . . . . . . . 141 5.1.15.4 cas bit-robbing (t1/j1, p access mode) . . . . . . . . . . . . . . . . . . . 141 5.1.15.5 bit oriented messages in esf-dl channel (t1/j1) . . . . . . . . . . . . 141 5.1.15.6 4 kbit/s data link access in f72 format (t1/j1) . . . . . . . . . . . . . . . 142 falc ? 56 pef 2256 h/e table of contents page user?s manual 6 ds1.1, 2003-10-23 hardware description 5.2 framer operating modes (t1/j1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 5.2.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 5.2.2 general aspects of synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . 143 5.2.3 addition for f12 and f72 format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 5.2.4 4-frame multiframe (f4 format, t1/j1) . . . . . . . . . . . . . . . . . . . . . . . 146 5.2.4.1 synchronization procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 5.2.5 12-frame multiframe (d4 or sf format, t1/j1) . . . . . . . . . . . . . . . . . 147 5.2.5.1 synchronization procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 5.2.6 extended superframe (f24 or esf format, t1/j1) . . . . . . . . . . . . . . . 148 5.2.6.1 synchronization procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 5.2.6.2 remote alarm (yellow alarm) generation/detection . . . . . . . . . . . . 150 5.2.6.3 crc6 generation and checking (t1/j1) . . . . . . . . . . . . . . . . . . . . . 150 5.2.7 72-frame multiframe (slc96 format, t1/j1) . . . . . . . . . . . . . . . . . . . 151 5.2.7.1 synchronization procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 5.2.8 summary of frame conditions (t1/j1) . . . . . . . . . . . . . . . . . . . . . . . . 154 5.3 additional receive framer functions (t1/j1) . . . . . . . . . . . . . . . . . . . . . 155 5.3.1 error performance monitoring and alarm handling . . . . . . . . . . . . . . . 155 5.3.2 auto modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 5.3.3 error counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 5.3.4 errored second . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 5.3.5 one-second timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 5.3.6 clear channel capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 5.3.7 in-band loop generation and detection . . . . . . . . . . . . . . . . . . . . . . . 158 5.3.8 transparent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 5.3.9 pulse-density detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 5.4 transmit path in t1/j1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 5.4.1 transmitter (t1/j1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 5.4.2 transmit line interface (t1/j1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 5.4.3 transmit jitter attenuator (t1/j1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 5.4.4 transmit elastic buffer (t1/j1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 5.4.5 programmable pulse shaper and line build-out (t1/j1) . . . . . . . . . . 165 5.4.6 transmit line monitor (t1/j1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 5.4.7 transmit signaling controller (t1/j1) . . . . . . . . . . . . . . . . . . . . . . . . . 167 5.4.7.1 hdlc or lapd access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 5.4.7.2 support of signaling system #7 . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 5.4.7.3 cas bit-robbing (t1/j1, serial mode) . . . . . . . . . . . . . . . . . . . . . . . 168 5.4.7.4 cas bit-robbing (t1/j1, p access mode) . . . . . . . . . . . . . . . . . . . 169 5.4.7.5 data link access in esf/f24 and f72 format (t1/j1) . . . . . . . . . . 169 5.4.7.6 periodical performance report in esf format (t1/j1) . . . . . . . . . . 169 5.5 system interface in t1/j1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 5.5.1 receive system interface (t1/j1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 5.5.1.1 receive offset programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 falc ? 56 pef 2256 h/e table of contents page user?s manual 7 ds1.1, 2003-10-23 hardware description 5.5.2 transmit system interface (t1/j1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 5.5.2.1 transmit offset programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 5.5.3 time slot assigner (t1/j1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 5.6 test functions (t1/j1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 5.6.1 pseudo-random binary sequence generation and monitor . . . . . . . . 188 5.6.2 remote loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 5.6.3 payload loop-back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 5.6.4 local loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 5.6.5 single channel loop-back (loop-back of time slots) . . . . . . . . . . . . . . 192 5.6.6 alarm simulation (t1/j1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 5.6.7 single bit defect insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 5.7 j1-feature overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 6 operational description e1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 6.1 operational overview e1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 6.2 device reset e1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 6.3 device initialization in e1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 6.4 digital clock interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 6.5 output signal tristate modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 7 operational description t1/j1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 7.1 operational overview t1/j1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 7.2 device reset t1/j1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 7.3 device initialization in t1/j1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 7.4 digital clock interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 7.5 output signal tristate modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 8 signaling controller operating modes . . . . . . . . . . . . . . . . . . . . . . . . 211 8.1 hdlc mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 8.1.1 non-auto mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 8.1.2 transparent mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 8.1.3 transparent mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 8.1.4 ss7 support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 8.1.5 receive data flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 8.1.6 transmit data flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 8.2 extended transparent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 8.3 signaling controller functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 8.3.1 transparent transmission and reception . . . . . . . . . . . . . . . . . . . . . . 215 8.3.2 crc on/off features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 8.3.3 receive address pushed to rfifo . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 8.3.4 hdlc data transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 8.3.5 hdlc data reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 8.3.6 sa-bit access (e1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 8.3.7 bit oriented message mode (t1/j1) . . . . . . . . . . . . . . . . . . . . . . . . . . 219 falc ? 56 pef 2256 h/e table of contents page user?s manual 8 ds1.1, 2003-10-23 hardware description 8.3.8 data link access in esf/f72 format (t1/j1) . . . . . . . . . . . . . . . . . . . 221 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 9 e1 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 9.1 e1 control register addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 9.2 detailed description of e1 control registers . . . . . . . . . . . . . . . . . . . . . 227 9.3 e1 status register addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 9.4 detailed description of e1 status registers . . . . . . . . . . . . . . . . . . . . . . 301 10 t1/j1 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 10.1 t1/j1 control register addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 10.2 detailed description of t1/j1 control registers . . . . . . . . . . . . . . . . . . . 348 10.3 t1/j1 status register addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424 10.4 detailed description of t1/j1 status registers . . . . . . . . . . . . . . . . . . . . 426 11 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464 11.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464 11.2 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465 11.3 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466 11.4 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469 11.4.1 master clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469 11.4.2 jtag boundary scan interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 11.4.3 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471 11.4.4 microprocessor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471 11.4.4.1 intel bus interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471 11.4.4.2 motorola bus interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475 11.4.5 line interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477 11.4.6 system interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480 11.4.7 pulse templates - transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492 11.4.7.1 pulse template e1 data interface . . . . . . . . . . . . . . . . . . . . . . . . . . 492 11.4.7.2 pulse template e1 synchronization interface . . . . . . . . . . . . . . . . . 493 11.4.7.3 pulse template t1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494 11.5 capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 11.6 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 11.7 test configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 11.7.1 ac tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 11.7.2 power supply test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497 12 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499 13 appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501 13.1 protection circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501 13.2 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501 13.3 software support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501 falc ? 56 pef 2256 h/e table of contents page user?s manual 9 ds1.1, 2003-10-23 hardware description terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509 index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514 falc ? 56 pef 2256 h/e list of figures page user?s manual 10 ds1.1, 2003-10-23 hardware description figure 1 gsm base station aplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 2 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 3 pin configuration p-mqfp-80-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 4 pin configuration p-lbga-81-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 6 fifo word access (intel mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 7 fifo word access (motorola mode) . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 8 interrupt status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 9 block diagram of test access port and boundary scan . . . . . . . . . . . 56 figure 10 jtag tap controller state machine . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 11 flexible master clock unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 12 single voltage power supply mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 13 dual voltage power supply mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 14 decoupling capacitor placement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 15 receive clock system (e1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 16 receiver configuration (e1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 17 receive line monitoring (e1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 18 short haul protection switching application (e1) . . . . . . . . . . . . . . . . 68 figure 19 long haul protection switching application (e1). . . . . . . . . . . . . . . . . 69 figure 20 jitter attenuation performance (e1). . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 21 jitter tolerance (e1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 22 the receive elastic buffer as circularly organized memory . . . . . . . 76 figure 23 automatic handling of errored signaling units . . . . . . . . . . . . . . . . . . 79 figure 24 2.048 mhz receive signaling highway (e1) . . . . . . . . . . . . . . . . . . . . 81 figure 25 crc4 multiframe alignment recovery algorithms (e1). . . . . . . . . . . . 92 figure 26 transmitter configuration (e1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 27 transmit clock system (e1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 figure 28 transmit line monitor configuration (e1) . . . . . . . . . . . . . . . . . . . . . 102 figure 29 2.048 mhz transmit signaling highway (e1) . . . . . . . . . . . . . . . . . . 104 figure 30 system interface (e1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 figure 31 receive system interface clocking (e1) . . . . . . . . . . . . . . . . . . . . . . 108 figure 32 sypr offset programming (2.048 mbit/s, 2.048 mhz) . . . . . . . . . . . 110 figure 33 sypr offset programming (8.192 mbit/s, 8.192 mhz) . . . . . . . . . . . 110 figure 34 rfm offset programming (2.048 mbit/s, 2.048 mhz) . . . . . . . . . . . . 111 figure 35 rfm offset programming (8.192 mbit/s, 8.192 mhz) . . . . . . . . . . . . 111 figure 36 transmit system interface clocking: 2.048 mhz (e1) . . . . . . . . . . . . 112 figure 37 transmit system interface clocking: 8.192 mhz/4.096 mbit/s (e1). . 113 figure 38 sypx offset programming (2.048 mbit/s, 2.048 mhz) . . . . . . . . . . . 115 figure 39 sypx offset programming (8.192 mbit/s, 8.192 mhz) . . . . . . . . . . . 115 figure 40 remote loop (e1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 figure 41 payload loop (e1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 figure 42 local loop (e1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 falc ? 56 pef 2256 h/e list of figures page user?s manual 11 ds1.1, 2003-10-23 hardware description figure 43 single channel loop-back (e1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 figure 44 receive clock system (t1/j1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 figure 45 receiver configuration (t1/j1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 figure 46 receive line monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 figure 47 protection switching application (t1/j1) . . . . . . . . . . . . . . . . . . . . . . 127 figure 48 long haul protection switching application (t1/j1) . . . . . . . . . . . . . 128 figure 49 jitter attenuation performance (t1/j1) . . . . . . . . . . . . . . . . . . . . . . . 131 figure 50 jitter tolerance (t1/j1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 figure 51 the receive elastic buffer as circularly organized memory . . . . . . 137 figure 52 automatic handling of errored signaling units . . . . . . . . . . . . . . . . . 140 figure 53 influences on synchronization status (t1/j1) . . . . . . . . . . . . . . . . . . 145 figure 54 transmitter configuration (t1/j1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 figure 55 clocking in remote loop configuration (t1/j1) . . . . . . . . . . . . . . . . 162 figure 56 transmit clock system (t1/j1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 figure 57 transmit line monitor configuration (t1/j1) . . . . . . . . . . . . . . . . . . . 167 figure 58 system interface (t1/j1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 figure 59 receive system interface clocking (t1/j1) . . . . . . . . . . . . . . . . . . . . 174 figure 60 sypr offset programming (1.544 mbit/s, 1.544 mhz) . . . . . . . . . . . 176 figure 61 sypr offset programming (6.176 mbit/s, 6.176 mhz) . . . . . . . . . . . 176 figure 62 rfm offset programming (1.544 mbit/s, 1.544 mhz) . . . . . . . . . . . . 177 figure 63 rfm offset programming (6.176 mbit/s, 6.176 mhz) . . . . . . . . . . . . 177 figure 64 2.048 mhz receive signaling highway (t1/j1). . . . . . . . . . . . . . . . . 178 figure 65 receive fs/dl-bits in time slot 0 on rdo (t1/j1) . . . . . . . . . . . . . 178 figure 66 1.544 mhz receive signaling highway (t1/j1). . . . . . . . . . . . . . . . . 179 figure 67 transmit system clocking: 1.544 mhz (t1/j1) . . . . . . . . . . . . . . . . . 180 figure 68 transmit system clocking: 8.192 mhz/4.096 mbit/s (t1/j1) . . . . . . . 181 figure 69 2.048 mhz transmit signaling clocking (t1/j1) . . . . . . . . . . . . . . . . 182 figure 70 1.544 mhz transmit signaling highway (t1/j1) . . . . . . . . . . . . . . . . 182 figure 71 signaling marker for cas/cas-cc applications (t1/j1) . . . . . . . . . . 183 figure 72 signaling marker for cas-br applications (t1/j1) . . . . . . . . . . . . . . 184 figure 73 transmit fs/dl bits on xdi (t1/j1) . . . . . . . . . . . . . . . . . . . . . . . . . 185 figure 74 sypx offset programming (1.544 mbit/s, 1.544 mhz) . . . . . . . . . . . 186 figure 75 sypx offset programming (6.176 mbit/s, 6.176 mhz) . . . . . . . . . . . 186 figure 76 remote loop (t1/j1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 figure 77 payload loop (t1/j1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 figure 78 local loop (t1/j1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 figure 79 channel loop-back (t1/j1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 figure 80 hdlc receive data flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 figure 81 hdlc transmit data flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 figure 82 interrupt driven data transmission (flow diagram) . . . . . . . . . . . . . . 217 figure 83 interrupt driven transmission example . . . . . . . . . . . . . . . . . . . . . . . 217 figure 84 interrupt driven reception sequence example . . . . . . . . . . . . . . . . . 218 falc ? 56 pef 2256 h/e list of figures page user?s manual 12 ds1.1, 2003-10-23 hardware description figure 85 mclk timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469 figure 86 jtag boundary scan timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 figure 87 reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471 figure 88 intel non-multiplexed address timing . . . . . . . . . . . . . . . . . . . . . . . . 471 figure 89 intel multiplexed address timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472 figure 90 intel read cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472 figure 91 intel write cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473 figure 92 motorola read cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475 figure 93 motorola write cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475 figure 94 digital line interface receive timing . . . . . . . . . . . . . . . . . . . . . . . . 477 figure 95 digital line interface transmit timing . . . . . . . . . . . . . . . . . . . . . . . . 477 figure 96 rclk and rfsp output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480 figure 97 sclkr/sclkx input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481 figure 98 receive system interface marker timing . . . . . . . . . . . . . . . . . . . . . 482 figure 99 sypr and sypx timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483 figure 100 transmit system interface marker timing . . . . . . . . . . . . . . . . . . . . . 485 figure 101 xdi and xsig timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486 figure 102 tclk input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487 figure 103 xclk timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488 figure 104 sec timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489 figure 105 fsc timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490 figure 106 sync timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491 figure 107 e1 pulse shape at transmitter output . . . . . . . . . . . . . . . . . . . . . . . 492 figure 108 dcim clock pulse shape at transmitter output . . . . . . . . . . . . . . . . 493 figure 109 t1 pulse shape at the cross connect point . . . . . . . . . . . . . . . . . . . 494 figure 110 thermal behavior of package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 figure 111 input/output waveforms for ac testing . . . . . . . . . . . . . . . . . . . . . . 496 figure 112 device configuration for power supply testing . . . . . . . . . . . . . . . . 497 figure 113 p-mqfp-80-1(plastic metric quad flat package) . . . . . . . . . . . . . . . 499 figure 114 p-lbga-81-1(plastic ball grid array package) . . . . . . . . . . . . . . . . . 500 figure 115 protection circuitry examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501 figure 116 master clock frequency calculator . . . . . . . . . . . . . . . . . . . . . . . . . . 503 figure 117 external line frontend calculator . . . . . . . . . . . . . . . . . . . . . . . . . . . 504 falc ? 56 pef 2256 h/e list of tables page user?s manual 13 ds1.1, 2003-10-23 hardware description table 1 pin definitions - microprocessor interface . . . . . . . . . . . . . . . . . . . . . . 26 table 2 pin definitions - line interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 3 pin definitions - clock interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 4 pin definitions - system interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 5 miscellaneous pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 6 data bus access (16-bit intel mode) . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 7 data bus access (16-bit motorola mode) . . . . . . . . . . . . . . . . . . . . . . 51 table 8 selectable bus and microprocessor interface configuration . . . . . . . . 52 table 9 tap controller instruction codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 10 decoupling capacitor parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 11 rclk output selection (e1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 12 recommended receiver configuration values (e1) . . . . . . . . . . . . . . 66 table 13 external component recommendations (monitoring) . . . . . . . . . . . . . 67 table 14 system clocking (e1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 15 output jitter (e1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 16 receive buffer operating modes (e1) . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 17 allocation of bits 1 to 8 of time slot 0 (e1) . . . . . . . . . . . . . . . . . . . . . 83 table 18 transmit transparent mode (doubleframe e1) . . . . . . . . . . . . . . . . . . 84 table 19 crc-multiframe structure (e1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 20 transmit transparent mode (crc multiframe e1) . . . . . . . . . . . . . . . 87 table 21 summary of alarm detection and release (e1) . . . . . . . . . . . . . . . . . 93 table 22 recommended transmitter configuration values (e1) . . . . . . . . . . . . 98 table 23 transmit buffer operating modes (e1) . . . . . . . . . . . . . . . . . . . . . . . 101 table 24 system clocking and data rates (e1) . . . . . . . . . . . . . . . . . . . . . . . 105 table 25 time slot assigner hdlc channel 1 (e1) . . . . . . . . . . . . . . . . . . . . . 116 table 26 rclk output selection (t1/j1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 table 27 recommended receiver configuration values (t1/j1). . . . . . . . . . . 125 table 28 external component recommendations (monitoring) . . . . . . . . . . . . 126 table 29 system clocking (t1/j1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 table 30 output jitter (t1/j1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 table 31 channel translation modes (ds1/j1) . . . . . . . . . . . . . . . . . . . . . . . . 135 table 32 receive buffer operation modes (t1/j1) . . . . . . . . . . . . . . . . . . . . . 136 table 33 resynchronization timing (t1/j1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 table 34 4-frame multiframe structure (t1/j1) . . . . . . . . . . . . . . . . . . . . . . . . 146 table 35 12-frame multiframe structure (t1/j1) . . . . . . . . . . . . . . . . . . . . . . . 147 table 36 extended superframe structure (f24, esf; t1/j1) . . . . . . . . . . . . . . 148 table 37 72-frame multiframe structure (t1/j1) . . . . . . . . . . . . . . . . . . . . . . . 152 table 38 summary frame recover/out of frame conditions (t1/j1) . . . . . . . 154 table 39 summary of alarm detection and release (t1/j1) . . . . . . . . . . . . . . 155 table 40 recommended transmitter configuration values (t1/j1). . . . . . . . . 160 table 41 transmit buffer operating modes (t1/j1) . . . . . . . . . . . . . . . . . . . . . 165 table 42 pulse shaper programming (t1/j1) . . . . . . . . . . . . . . . . . . . . . . . . . 165 falc ? 56 pef 2256 h/e list of tables page user?s manual 14 ds1.1, 2003-10-23 hardware description table 43 structure of periodical performance report (t1/j1) . . . . . . . . . . . . . 170 table 44 bit functions in periodical performance report . . . . . . . . . . . . . . . . 171 table 45 system clocking and data rates (t1/j1) . . . . . . . . . . . . . . . . . . . . . 172 table 46 time slot assigner hdlc channel 1 (t1/j1) . . . . . . . . . . . . . . . . . . 187 table 47 initial values after reset (e1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 table 48 initialization parameters (e1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 table 49 line interface initialization (e1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 table 50 framer initialization (e1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 table 51 hdlc controller initialization (e1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 table 52 cas-cc initialization (e1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 table 53 output tristate programming (e1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 table 54 initial values after reset and fmr1.pmod = 1 (t1/j1) . . . . . . . . . . . 203 table 55 initialization parameters (t1/j1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 table 56 line interface initialization (t1/j1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 table 57 framer initialization (t1/j1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 table 58 hdlc controller initialization (t1/j1) . . . . . . . . . . . . . . . . . . . . . . . . 209 table 59 initialization of the cas-br controller (t1/j1). . . . . . . . . . . . . . . . . . 209 table 60 output tristate programming (t1/j1) . . . . . . . . . . . . . . . . . . . . . . . . 210 table 61 e1 control register address arrangement . . . . . . . . . . . . . . . . . . . . 223 table 62 dco-r and dco-x corner frequency programing (e1) . . . . . . . . . 274 table 63 transmit cas registers (e1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 table 64 gcmx register programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 table 65 e1 status register address arrangement . . . . . . . . . . . . . . . . . . . . . 299 table 66 receive cas registers (e1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 table 67 t1/j1 control register address arrangement . . . . . . . . . . . . . . . . . . 344 table 68 pulse shaper programming (t1/j1) . . . . . . . . . . . . . . . . . . . . . . . . . 377 table 69 dco-r and dco-x corner frequency programing (t1/j1) . . . . . . . 400 table 70 transmit signaling registers (t1/j1). . . . . . . . . . . . . . . . . . . . . . . . . 401 table 71 gcmx register programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418 table 72 t1/j1 status register address arrangement . . . . . . . . . . . . . . . . . . 424 table 73 alarm simulation states. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432 table 74 receive signaling registers (t1/j1) . . . . . . . . . . . . . . . . . . . . . . . . . 456 table 75 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464 table 76 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465 table 77 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466 table 78 mclk timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469 table 79 boundary scan timing parameter values . . . . . . . . . . . . . . . . . . . . . 470 table 80 reset timing parameter values . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471 table 81 intel bus interface timing parameter values . . . . . . . . . . . . . . . . . . 474 table 82 motorola bus interface timing parameter values . . . . . . . . . . . . . . . 476 table 83 digital line interface timing parameter values. . . . . . . . . . . . . . . . . 478 table 84 rclk and rfsp timing parameter values . . . . . . . . . . . . . . . . . . . 480 falc ? 56 pef 2256 h/e list of tables page user?s manual 15 ds1.1, 2003-10-23 hardware description table 85 sclkr/sclkx timing parameter values. . . . . . . . . . . . . . . . . . . . . 481 table 86 receive system interface marker timing parameter values . . . . . . 482 table 87 sypr and sypx timing parameter values . . . . . . . . . . . . . . . . . . . 483 table 88 transmit system interface marker timing parameter values . . . . . . 485 table 89 xdi and xsig timing parameter values . . . . . . . . . . . . . . . . . . . . . . 486 table 90 tclk timing parameter values . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487 table 91 xclk timing parameter values . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488 table 92 sec timing parameter values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489 table 93 fsc timing parameter values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490 table 94 sync timing parameter values . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491 table 95 e1 pulse amplitude values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492 table 96 dcim pulse output amplitude values . . . . . . . . . . . . . . . . . . . . . . . . 493 table 97 t1 pulse template at cross connect point (t1.102) . . . . . . . . . . . . 494 table 98 capacitance values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 table 99 package characteristic values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 table 100 ac test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 table 101 power supply test conditions e1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 497 table 102 power supply test conditions t1/j1 . . . . . . . . . . . . . . . . . . . . . . . . . 498 falc ? 56 pef 2256 h/e user?s manual 16 ds1.1, 2003-10-23 hardware description preface the falc ? 56 framer and line interface component is designed to fulfill all required interfacing between an analog e1/t1/j1 line and the digital pcm system highway/h.100 bus. the digital functions as well as the analog characteristics are configured via a flexible microprocessor interface. organization of this document this user?s manual is organized as follows: chapter 1 , introduction gives a general description of the product and its family, lists the key features, and presents some typical applications. chapter 2 , external signals lists pin locations with associated signals, categorizes signals according to function, and describes signals. chapter 3 to chapter 5 , functional description e1/t1/j1 these chapters describe the functional blocks and principle operation modes, organized into separate sections for e1 and t1/j1 operation chapter 6 and chapter 7 , operational description e1/t1/j1 shows the operation modes and how they are to be initialized (separately for e1 and t1/j1). chapter 8 , signaling controller operating modes describes signaling controller functions for both e1 and t1/j1 operation. chapter 9 and chapter 10 , e1 registers and t1/j1 registers gives a detailed description of all implemented registers and how to use them in different applications/configurations. chapter 11 , electrical characteristics specifies maximum ratings, dc and ac characteristics. chapter 12 , package outlines shows the mechanical values of the device packages. chapter 13 , appendix gives an example for overvoltage protection and information about application notes and other support. terminology references index falc ? 56 pef 2256 h/e introduction user?s manual 17 ds1.1, 2003-10-23 hardware description 1 introduction the falc ? 56 framer and line interface component is designed to fulfill all required interfacing between analog e1/t1/j1 lines and the digital pcm system highway, h.100/h.110 or h-mvip bus for world market telecommunication systems. due to its multitude of implemented functions, it fits to a wide range of networking applications and fulfills the according international standards. three integrated signaling controllers including signaling system #7 (ss7) support reduces software overhead. crystal-less jitter attenuation with only one master clock source, integrated receive line termination, and an analog switch reduce t he amount of required external components. equipped with a flexible microprocessor interface, it connects to any control processor environment. a standard boundary scan interface is provided to support board level testing. flat pack or bga device packaging, minimum number of external components and low power consumption lead to reduced overall system costs. type package pef 2256 h p-mqfp-80-1 pef 2256 e p-lbga-81-1 e1/t1/j1 framer and line interface component for long- and short-haul applications falc ? 56 pef 2256 h/e user?s manual 18 ds1.1, 2003-10-23 hardware description version 2.1 1.1 features line interface high-density, generic interface for all e1/t1/j1 applications analog receive and transmit circuits for long-haul and short-haul applications e1 or t1/j1 mode selectable data and clock recovery using an integrated digital phase-locked loop maximum line attenuation up to -43 db at 1024 khz (e1) and up to -36 db at 772 khz (t1/j1) programmable receive equalizer characteristic software-selectable receive line termination programmable transmit pulse shapes for e1 and t1/j1 pulse masks programmable line build-out for csu signals according to ansi t1. 403 and fcc68: 0db, -7.5 db, -15 db, -22.5 db (t1/j1) low transmitter output impedances for high transmit return loss tristate function of the analog transmit line outputs analog switch for redundancy applications transmit line monitor protecting the device from damage receive line monitor mode jitter specifications of itu-t i.431, g.703, g.736 (e1), g.823 (e1) and at&t tr62411 (t1/j1) are met crystal-less wander and jitter attenuation/compensation p-mqfp-80-1 p-lbga-81-1 falc ? 56 pef 2256 h/e introduction user?s manual 19 ds1.1, 2003-10-23 hardware description common master clock reference for e1 and t1/j1 (any frequency within 1.02 and 20 mhz) power-down function support of automatic protection switching dual-rail or single-rail digital inputs and outputs unipolar nrz or cmi for interfacing fiber-optical transmission routes selectable line codes (e1: hdb3, ami/t1: b8zs, ami with zcs) loss-of-signal indication with programmable thresholds according to itu-t g.775, ets300233 (e1) and ansi t1.403 (t1/j1) optional data stream muting upon los detection programmable receive slicer threshold clock generator for jitter-free system/transmit clocks per channel local loop and remote loop for diagnostic purposes low power device single power supply (3.3 v) or dual power supply (3.3 v and 1.8 v) frame aligner frame alignment/synthesis for 2048 kbit/s according to itu-t g.704 (e1) and for 1544 kbit/s according to itu-t g.704 and jt g.704 (t1/j1) programmable frame formats: e1: doubleframe, crc multiframe (e1) t1: 4-frame multiframe (f4,ft), 12-frame multiframe (f12, d3/4), extended superframe (f24, esf), remote switch mode (f72, slc96) selectable conditions for recover/loss of frame alignment crc4 to non-crc4 interworking according to itu-t g. 706 annex b (e1) error checking via crc4 procedures according to itu-t g. 706 (e1) error checking via crc6 procedures acco rding to itu-t g. 706 and jt g.706 (t1/j1) performs synchronization in esf format according to ntt requirements (j1) alarm and performance monitoring per second 16 bit counter for crc-errors, framing erro rs, code violations, error monitoring via e-bit and sa6-bit (e1), errored blocks, prbs bit errors insertion and extraction of alarm indication signals (ais, remote/yellow alarm,?) remote alarm generation/checking according to itu jt-g.704 in esf-format (j1) idle code insertion for selectable channels single-bit defect insertion flexible system clock frequency for receiver and transmitter supports programmable system data rates with independent receive/transmit shifts: e1: 2.048, 4.096, 8.192 and 16.384 mbit/s (according to h.100/h.110 bus) t1/j1: 2.048, 4.096, 8.192, 16.384 mbit/s and 1.544, 3.088, 6.176, 12.352 mbit/s elastic store for receive and transmit route clock wander and jitter compensation; controlled slip capability and slip indication falc ? 56 pef 2256 h/e introduction user?s manual 20 ds1.1, 2003-10-23 hardware description programmable elastic buffer size: 2 frames/1 frame/short buffer/bypass provides different time slot mapping modes supports fractional e1 or t1/j1 access flexible transparent modes programmable in-band loop code detection and generation (tr62411) channel loop back, line loop back or payload loop back capabilities (tr54016) pseudo-random binary sequence generator and monitor (framed or unframed) clear channel capabilities (t1/j1) loop-timed mode signaling controller three hdlc controllers bit stuffing, crc check and generation, flag generation, flag and address recognition, handling of bit oriented functions each hdlc controller selectable to operate on either line or system side supports signaling system #7 delimitation, alignment and error detection according to itu-q.703 processing of fill in signaling units, processing of errored signaling units cas/cas-br controller with last look capability, enhanced cas-register access and freeze signaling indication dl-channel protocol for esf format according to ansi t1.403 specification or according to at&t tr54016 (t1/j1) dl-bit access for f72 (slc96) format (t1/j1) generates periodical performance report according to ansi t1. 403 provides access to serial signaling data streams multiframe synchronization and synthesis according to itu-t g.732 alarm insertion and detection (ais and los in time slot 16) transparent mode fifo buffers (64 bytes deep) for efficient transfer of data packets time slot assignment any combination of time slots selectable for data transfer independent of signaling mode (useful for fractional t1/j1 applications) time-slot 0 s a 8...4-bit handling via fifos (e1) hdlc access to any s a -bit combination (e1) microprocessor interface 8/16-bit microprocessor bus interface (intel or motorola type) all registers directly accessible (byte or word access) multiplexed and non-multiplexed address bus operations hard/software reset options extended interrupt capabilities falc ? 56 pef 2256 h/e introduction user?s manual 21 ds1.1, 2003-10-23 hardware description one-second timer (internal or external timing reference) general general input/output function included in multifunction ports boundary scan standard ieee 1149.1 p-lbga-81-1 package; body size 10 mm 10 mm; ball pitch 1.0 mm or p-mqfp-80-1 package; body size 14 mm 14 mm; lead pitch 0.5 mm temperature range from -40 to +85 c 3.3 v and 1.8 v power supply or 3.3 v-only operation typical power consumption 250 mw applications wireless basestations e1/t1/j1 atm gateways, multiplexer e1/t1/j1 c hannel & d ata s ervice u nits (csu, dsu) e1/t1/j1 internet access equipment lan/wan router isdn pri, pabx d igital a ccess c rossconnect s ystems (dacs) sonet/sdh add/drop multiplexer falc ? 56 pef 2256 h/e introduction user?s manual 22 ds1.1, 2003-10-23 hardware description 1.2 typical applications figure 1 shows a typical application used in gsm base stations. figure 1 gsm base station aplication f56v2_application_1 falc56 mi c ro- processor falc56 epi c epi c munich 32/256 rs485 rs485 e1/t1/j1 e1/t1/j1 serocco serocco 2306+2312 2306+2312 dsp dsp rs485 rs485 serocco serocco 2306+2312 2306+2312 dsp dsp rs485 rs485 falc ? 56 pef 2256 h/e external signals user?s manual 23 ds1.1, 2003-10-23 hardware description 2 external signals 2.1 logic symbol figure 2 logic symbol f56v2_logic_symbol sclkr rdo rpa rpb rpc rpd 4 4 4 4 sclkx xdi xpa xpb xpc xpd 4 4 4 4 rl1/rdip/roid rl2/rdin/rclki xl1/xdop/xoid xl2/xdon trs tdi tms tck tdo v dd v ss rclk mclk sync clk1 clk2 sec/fsc 15 d(15:0) a(7:0) 8 cs wr/rw rd/ds bhe/ble ale dbw im int res v ddc vsel as1 as2 falc ? 56 pef 2256 v ddp v ddr v ddx falc ? 56 pef 2256 h/e external signals user?s manual 24 ds1.1, 2003-10-23 hardware description 2.2 pin diagram p-mqfp-80-1 figure 3 pin configuration p-mqfp-80-1 f56v2_pin_configuration_pmqfp8 0 xpb rpa rdo sclkr sclkx xpd xpc xpa a2 a3 a4 a5 a6 a7 ale rd/ ds wr/rw cs bhe/ble xdi int v dd v ss v dd v ss a0 a1 d0 v dd v ss d4 d3 d2 d1 41 44 48 52 56 60 36 40 64 61 vsel sync sec/fsc d15 d14 d13 v ss tms td i trs res dbw im v ss v ddp v ss xl1/xdop/xoid v ddx xl2/xdon v ddr rl1/rdip/roid rl2/rdin/rclki as2 as1 tdo tck 21 80 14 8 12 16 20 clk1 rclk mclk v ss v dd rpd rpc rpb clk2 v ss d12 d11 d10 d9 d8 d7 d6 d5 v dd 24 28 32 76 72 68 v ddc top view falc ? 56 pef 2256 falc ? 56 pef 2256 h/e external signals user?s manual 25 ds1.1, 2003-10-23 hardware description 2.3 pin diagram p-lbga-81-1 figure 4 pin configuration p-lbga-81-1 f56v2_pin_configuration_plbga8 1 2 1 3456789 sync rclk v dd rpb sclkr xpc xpb v ss sec/ fsc clk1 rpc rdo xpd xpa v ss rl2/ rdin rl1/ rdip clk2 mc lk v ss sclkx int v dd bhe/ ble xl2/ xdon v ddx v ddr xl1/ xdop rpd rpa wr/rw xdi cs v ss v ddp dbw v ss n.c. a7 rd/ds a6 ale im tms res d11 d8 a4 a1 a3 a5 trs tdo tck v dd d6 d5 d3 a0 a2 tdi d13 d12 d9 d4 d2 d0 v ss d14 d10 d7 d1 v dd d15 a b c d e f g h j top view v ddc vsel as1 as2 v dd v ss v ss falc ? 56 pef 2256 h/e external signals user?s manual 26 ds1.1, 2003-10-23 hardware description 2.4 pin description this chapter describes the pin functions. there is no functional difference between tqfp and bga package. pin numbers refer to the tqpp package while the ball numbers refer to the bga package. 2.4.1 input/output signals table 1 pin definitions - microprocessor interface pin or ball no. name pin type buffer type function 50 (e6) a7 i pu address bus these inputs interface with eight bits of the system?s address bus to select one of the internal registers for read or write. 49 (e8) a6 48 (f9) a5 47 (f6) a4 46 (f8) a3 45 (g9) a2 44 (f7) a1 43 (g8) a0 21 (j1) d15 i/o pu data bus bidirectional tristate data lines which interface with the system?s data bus. their configuration is controlled by the level of pin dbw (data bus width), output drivers are controlled by wr /rw (write enable or read/write selection). 22 (j2) d14 23 (h3) d13 26 (h4) d12 27 (f4) d11 28 (j4) d10 29 (h5) d9 30 (f5) d8 31 (j5) d7 32 (g5) d6 33 (g6) d5 36 (h6) d4 37 (g7) d3 38 (h7) d2 39 (j8) d1 40 (h8) d0 falc ? 56 pef 2256 h/e external signals user?s manual 27 ds1.1, 2003-10-23 hardware description 51 (e9) ale i pu address latch enable this signal allows the falc ? 56 to be connected to a multiplexed address/data bus without the need for external latches. the address information provided on lines a(7:0) is internally latched with the falling edge of ale. in this application, pins a(7:0) must be connected to the data bus pins externally. in case of demultiplexed mode this pin can be connected directly to v dd or can be left open. 52 (e7) rd ipu read enable used in intel bus mode. this signal indicates a read operation. when the falc ? 56 is selected via cs , the rd signal enables the bus drivers to output data from an internal register addressed by a(7:0) to the data bus. ds ipu data strobe used in motorola bus mode. this pin serves as input to control read/write operations. 53 (d7) wr ipu write enable used in intel bus mode. this signal indicates a write operation. when cs is active the falc ? 56 loads an internal register with data provided on the data bus. rw ipu read/write enable used in motorola bus mode. this signal distinguishes between read and write operations. table 1 pin definitions - microprocessor interface (cont?d) pin or ball no. name pin type buffer type function falc ? 56 pef 2256 h/e external signals user?s manual 28 ds1.1, 2003-10-23 hardware description 12 (e3) dbw i pu data bus width this input signal selects the bus interface mode. 0 b dbw_0 , 8-bit mode, d(7:0) are active. d(15:8) are internally pulled high and can be left open. 1 b dbw_1 , 16-bit mode, d(15:0) are active. word transfer to/from the internal registers is enabled. in case of byte transfers, the active half of the bus is determined by a0 and bhe /ble and the selected bus interface mode (via pin im). the unused half is internally pulled high. 11 (e1) im i pu interface mode the level on this pin defines the bus interface mode. 0 b im_0 , intel bus interface mode. 1 b im_1 , motorola bus interface mode. 54 (d9) cs ipu chip select a low signal selects the falc ? 56 for read and write operations. this allows to connect multiple devices to a single data/address bus. 0 b cs_0 , device is selected for access. 1 b cs_1 , device is de-selected. table 1 pin definitions - microprocessor interface (cont?d) pin or ball no. name pin type buffer type function falc ? 56 pef 2256 h/e external signals user?s manual 29 ds1.1, 2003-10-23 hardware description 55 (c9) bhe ipu bus high enable used in intel bus mode. if 16-bit bus interface mode is enabled, this signal indicates a data transfer on the upper byte of the data bus d(15:8). in 8-bit bus interface mode this signal has no function and should be tied to v dd or left open. ble ipu bus low enable used in motorola bus mode. if 16-bit bus interface mode is enabled, this signal indicates a data transfer on the lower byte of the data bus d(7:0). in 8-bit bus interface mode this signal has no function and should be tied to v dd or left open 57 (c7) int o od/pp interrupt request this signal serves as general interrupt request for all interrupt sources. these interrupt sources can be masked via registers imr(5:0). interrupt status is reported via registers gis (global interrupt status) and isr(5:0). output characteristics (push-pull active low/high, open drain) are determined by programming register ipc. table 1 pin definitions - microprocessor interface (cont?d) pin or ball no. name pin type buffer type function falc ? 56 pef 2256 h/e external signals user?s manual 30 ds1.1, 2003-10-23 hardware description table 2 pin definitions - line interface pin or ball no. name pin type buffer type function 3 (c2) rl1 i analog line receiver input 1 analog input from the external transformer. selected by lim1.drs = 0. rdip i digital receive data input positive digital input for received dual-rail pcm(+) route signal which is latched with the internally recovered receive route clock. an internal dpll extracts the receive route clock from the incoming data pulses. the duty cycle of the received signal has to be close to 50%. the dual-rail mode is selected if lim1.drs = 1 b and fmr0.rc1 = 1 b . input polarity is selected by bit rc0.rdis (active low by default), line coding is selected by fmr0.rc(1:0). roid i digital receive optical interface data unipolar data received from a fiber-optical interface. latching of data is done with the falling edge of rclki. input polarity is selected by bit rc0.rdis. the single-rail mode is selected if lim1.drs = 1 b and fmr0.rc1 = 0 b . if cmi coding is selected (fmr0.rc(1:0) = 01 b ), an internal dpll recovers clock and data, no clock signal on rclki is required. falc ? 56 pef 2256 h/e external signals user?s manual 31 ds1.1, 2003-10-23 hardware description 2 (b1) rl2 i analog line receiver input 2 analog input from the external transformer. selected by lim1.drs = 0 b . rdin i digital receive data input negative digital input for received dual-rail pcm(-) route signal which is latched with the internally recovered receive route clock. an internal dpll extracts the receive route clock from the incoming data pulses. the duty cycle of the received signal has to be close to 50%. the dual-rail mode is selected if lim1.drs = 1 b and fmr0.rc1 = 1 b . input polarity is selected by bit rc0.rdis (active low by default), line coding is selected by fmr0.rc(1:0) rclki i digital receive clock input receive clock input for the optical interface if lim1.drs = 1 b and fmr0.rc(1:0) = 00 b . the clock frequency is 2.048 mhz (e1) or 1.544 mhz (t1/j1). rclki is ignored if cmi coding is selected. table 2 pin definitions - line interface (cont?d) pin or ball no. name pin type buffer type function falc ? 56 pef 2256 h/e external signals user?s manual 32 ds1.1, 2003-10-23 hardware description 7 (d4) xl1 o analog transmit line 1 analog output to the external transformer. selected if lim1.drs = 0 b . after reset this pin is in high-impedance state until bit fmr0.xc1 = 1 b and xpm2.xlt = 0 b . more details about tristate modes are shown in table 53 / table 60 . xdop o digital transmit data output positive this digital output for transmitted dual-rail pcm(+) route signals can provide half bauded signals with 50% duty cycle (lim0.xfb = 0 b ) or full bauded signals with 100% duty cycle (lim0.xfb = 1 b ) the data is clocked with positive transitions of xclk in both cases. output polarity is selected by bit lim0.xdos (active low by default). the dual-rail mode is selected if lim1.drs = 1 b and fmr0.xc1 = 1 b . after reset this pin is in high-impedance state until register lim1.drs = 1 b and xpm2.xlt = 0 b . xoid o digital transmit optical interface data unipolar data sent to a fiber-optical interface with 2048 kbit/s (e1) or 1544 kbit/s (t1/j1) which is clocked on the positive transitions of xclk. clocking of nrz-coded data is done with 100% duty cycle. cmi-coded data is shifted out with 50 % or 100 % duty cycle on both transitions of xclk according to the cmi coding. output polarity is selected by bit lim0.xdos (active high by default). the single-rail mode is selected if lim1.drs = 1 b and fmr0.xc1 = 0 b . after reset this pin is in high-impedance state until register lim1.drs = 1 b and xpm2.xlt = 0 b . table 2 pin definitions - line interface (cont?d) pin or ball no. name pin type buffer type function falc ? 56 pef 2256 h/e external signals user?s manual 33 ds1.1, 2003-10-23 hardware description 5 (c1) xl2 o analog transmit line 2 analog output to the external transformer. selected if lim1.drs = 0 b . after reset this pin is in high-impedance state until bit fmr0.xc1 = 1 b and xpm2.xlt = 0 b . more details about tristate modes are shown in table 53 / table 60 . xdon o digital transmit data output negative this digital output for transmitted dual-rail pcm(-) route signals can provide half bauded signals with 50% duty cycle (lim0.xfb = 0 b ) or full bauded signals with 100% duty cycle (lim0.xfb = 1 b ) the data is clocked with positive transitions of xclk in both cases. output polarity is selected by bit lim0.xdos (active low by default). the dual-rail mode is selected if lim1.drs = 1 b and fmr0.xc1 = 1 b . after reset this pin is in high-impedance state until register lim1.drs = 1 b and xpm2.xlt = 0 b . xfm o digital transmit frame marker this digital output marks the first bit of every frame transmitted on port xdop. this function is only available in the optical interface mode (lim1.drs = 1 b and fmr0.xc1 = 0 b ). data is clocked on positive transitions of xclk. after reset this pin is in high-impedance state until register lim1.drs = 1 b and xpm2.xlt = 0 b . note: in remote loop configuration the xfm marker is not valid. table 2 pin definitions - line interface (cont?d) pin or ball no. name pin type buffer type function falc ? 56 pef 2256 h/e external signals user?s manual 34 ds1.1, 2003-10-23 hardware description table 3 pin definitions - clock interface pin or ball no. name pin type buffer type function 73 (c4) mclk i master clock a reference clock of better than 32 ppm accuracy in the range of 1.02 to 20 mhz must be provided on this pin. the falc ? 56 internally derives all necessary clocks from this master (see registers gcm(8:1) for more detail). 79 (a2) sync i pu clock synchronization of dco-r if a clock is detected on pin sync the dco-r circuitry of the falc ? 56 synchronizes to this 1.544/2.048 mhz clock (see lim0.mas, cmr1.dcs and cmr2.dcf). additionally, in master mode the falc ? 56 is able to synchronize to an 8-khz reference clock (ipc.ssyf = 1). 76 (b4) clk1 o pu dco-r clock output output of the de-jittered system clock generated by the dco-r circuit. frequency selection is done by setting control bits in pc5/6. selectable frequencies are: e1: 16.384 mhz, 8.192 mhz, 4.096 mhz, 2.048 mhz or 8 khz t1/j1: 16.384 mhz, 12.352 mhz, 8.192 mhz, 6.176 mhz, 4.096 mhz, 3.088 mhz, 2.048 mhz, 1.544 mhz or 8 khz after reset this output is inactive and internally pulled high. note: if dco-r is not active (sic1.rbs(1:0) = 11 b and cmr1.rs1 = 0 b ), no clock is driven on pin clk1. falc ? 56 pef 2256 h/e external signals user?s manual 35 ds1.1, 2003-10-23 hardware description 77 (c3) clk2 o pu dco-x clock output output of the de-jittered system clock generated by the dco-x circuit. frequency selection is done by setting control bits in pc5/6. selectable frequencies are: e1: 16.384 mhz, 8.192 mhz, 4.096 mhz or 2.048 mhz t1/j1: 12.352 mhz, 6.176 mhz, 3.088 mhz or 1.544 mhz after reset this output is inactive and internally pulled high. note: if dco-x is not used, no clock is driven on pin clk2 (sic1.xbs(1:0) = 00 b and cmr1.dxja = 1 b ; buffer bypass and no jitter attenuation) table 3 pin definitions - clock interface (cont?d) pin or ball no. name pin type buffer type function falc ? 56 pef 2256 h/e external signals user?s manual 36 ds1.1, 2003-10-23 hardware description 78 (b3) sec i pu one-second timer reference input a pulse with logical high level for at least two line clock cycles triggers the internal one-second timer. after reset this pin is configured to be an input. see register gpc1 for more detail. o one-second timer output activated high once every second for the duration of two line clock cycles. fsc o frame synchronization pulse an 8-khz frame synchronization pulse is output on this pin. the synchronization pulse is active high or active low for one 2.048/1.544 mhz cycle ( e1 or t1/j1). fsc can be switched into tri-state mode (sic3.fsct) table 3 pin definitions - clock interface (cont?d) pin or ball no. name pin type buffer type function falc ? 56 pef 2256 h/e external signals user?s manual 37 ds1.1, 2003-10-23 hardware description 75 (a3) rclk o pu receive clock after reset this port is configured to be internally pulled up weakly. setting of bit pc5.crp switches this port to be an active output. several output modes are provided, selected by cmr1.rs(1:0). cmr1.rs(1:0) = 00 b : receive clock extracted from the incoming data pulses. the clock frequency is 2.048 mhz (e1) or 1.544 mhz (t1/j1). in case of l oss- o f- s ignal (los) the output is derived from the clock that is provided on mclk. cmr1.rs(1:0) = 01 b : receive clock extracted from the incoming data pulses. the clock frequency is 2.048 mhz (e1) or 1.544 mhz (t1/j1). rclk remains high in case of los (as indicated by frs0.los = 1 b ). cmr1.rs(1:0) = 10 b : dejittered clock generated by the internal dco-r circuit. the clock frequency is 2.048 mhz (e1/t1/j1 and sic2.ssc2 = 0 b ) or 1.544 mhz (t1/j1 and sic2.ssc2 = 1 b ). cmr1.rs(1:0) = 11 b : dejittered clock generated by the internal dco-r circuit. the clock frequency is 8.192 mhz (e1/t1/j1 and sic2.ssc2 = 0 b ) or 6.176 mhz (t1/j1 and sic2.ssc2 = 1 b ). table 3 pin definitions - clock interface (cont?d) pin or ball no. name pin type buffer type function falc ? 56 pef 2256 h/e external signals user?s manual 38 ds1.1, 2003-10-23 hardware description table 4 pin definitions - system interface pin or ball no. name pin type buffer type function 66 (b6) rdo o receive data output received data that is sent to the system highway. clocking of data is done with the rising or falling edge (sic3.resr) of sclkr or rclk, if the receive elastic store is bypassed. the delay between the beginning of time slot 0 and the initial edge of sclkr (after sypr goes active) is determined by the values of registers rc1 and rc0. if received data is shifted out with higher data rates (more than 2.048/1.544 mbit/s), the active channel phase is defined by bits sic2.sics(2:0). during inactive channel phases rdo is cleared (driven to low level or tristate, see sic3.rtri on page 267 / 393 ). 65 (a7) sclkr i/o pu receive system clock working clock for the receive system interface with a frequency of 16.384/8.192/4.096/2.048 mhz in e1 mode and 16.384/8.192/4.096/2.048 mhz (sic2.ssc2 = 0 b ) or 12.352/6.176/3.088/1.544 mhz (sic2.ssc2 = 1 b ) in t1/j1 mode. if the receive elastic store is bypassed, the clock supplied on this pin is ignored, because rclk is used to clock the receive system interface. if sclkr is configured to be an output, the internal working clock of the receive system interface sourced by dco-r or rclk is output. falc ? 56 pef 2256 h/e external signals user?s manual 39 ds1.1, 2003-10-23 hardware description 67 (d6) 68 (a6) 69 (b5) 70 (d5) rpa rpb rbc rpd receive multifunction ports depending on programming of bits pc(1:4).rpc(3:0) these multifunction ports carry information to the system interface or from the system to the falc ? 56. after reset these ports are configured to be inputs. with the selection of the appropriate pin function, the corresponding input/output configuration is achieved automatically. depending on bit sic3.resr latching/transmission of data is done with the rising or falling edge of sclkr. the same input function must not be selected twice or more. selectable pin functions are described below. ipu synchronous pulse receive (sypr ) pc(1:4).rpc(3:0) = 0000 b together with the values of registers rc(1:0) this signal defines the beginning of time slot 0 on system highway port rdo. only one multifunction port may be selected as sypr input. after reset, sypr of port a is used, the other lines are ignored. sypr cannot be used in combination with rfm. the pulse cycle is an integer multiple of 125 s. table 4 pin definitions - system interface (cont?d) pin or ball no. name pin type buffer type function falc ? 56 pef 2256 h/e external signals user?s manual 40 ds1.1, 2003-10-23 hardware description 67 (d6) 68 (a6) 69 (b5) 70 (d5) rpa rpb rbc rpd o receive frame marker (rfm) pc(1:4).rpc(3:0) = 0010 b two different modes are provided for this signal, selected by cmr2.irsp. 0 b irsp_0 , the receive frame marker can be active high for a 2.048 mhz (e1) or 1.544 mhz (t1/j1) period during any bit position of the current frame. it is clocked off with the rising or falling edge of sclkr or rclk, depending on sic3.resr. offset programming is done by using registers rc(1:0). 1 b irsp_1 , frame synchronization pulse generated by the dco-r circuitry internally. together with registers rc(1:0) the frame begin on the receive system interface is defined. this frame synchronization pulse is active low for a 2.048 mhz (e1) or 1.544 mhz (t1/j1) period. o receive multiframe begin (rmfb) pc(1:4).rpc(3:0) = 0010 b in e1 mode rmfb marks the beginning of every received multiframe (rdo). optionally the time slot 16 cas multiframe begin can be marked (sic3.casmf). active high for one 2.048 mhz period. in t1/j1 mode the function depends on bit xc0.mfbs: 0 b mfbs_0 , rmfb marks the beginning of every received multiframe (rdo). 1 b mfbs_1 , rmfb marks the beginning of every received superframe. additional pulses are provided every 12 frames when using esf/f24 or f72 format. table 4 pin definitions - system interface (cont?d) pin or ball no. name pin type buffer type function falc ? 56 pef 2256 h/e external signals user?s manual 41 ds1.1, 2003-10-23 hardware description 67 (d6) 68 (a6) 69 (b5) 70 (d5) rpa rpb rbc rpd o receive signaling marker (rsigm) pc(1:4).rpc(3:0) = 0011 b e1: marks the time slots which are defined by register rtr(4:1) of every received frame on port rdo. t1/j1: the function depend on the usage of cas-br as selected by xc0.brm. 0 b brm_0 , marks the time slots which are defined by register rtr(4:1) of every received frame on port rdo. 1 b brm_1 , the robbed bit of each channel in every sixth frame is marked. o receive signaling data (rsig) pc(1:4).rpc(3:0) = 0100 b the received cas signaling data is sourced by this pin. time slots on rsig correlate directly to the time slot assignment on rdo. o data link bit receive (dlr) pc(1:4).rpc(3:0) = 0101 b e1: marks the s a (8:4)-bits within the data stream on rdo. the s a (8:4)-bit positions in time slot 0 of every frame not containing the frame alignment signal are selected by register xc0. t1/j1: marks the dl-bit position within the data stream on rdo. o frame synchronous pulse (rfsp ) pc(1:4).rpc(3:0) = 0111 b active low framing pulse derived from the received pcm route signal (line side, rclk). during loss of synchronization (bit frs0.lfa = 1 b ), this pulse is suppressed (not influenced during alarm simulation). pulse frequency: 8 khz pulse width: 488 ns (e1) or 648 ns (t1/j1). table 4 pin definitions - system interface (cont?d) pin or ball no. name pin type buffer type function falc ? 56 pef 2256 h/e external signals user?s manual 42 ds1.1, 2003-10-23 hardware description 67 (d6) 68 (a6) 69 (b5) 70 (d5) rpa rpb rbc rpd o loss of signal indication (los) pc(1:4).rpc(3:0) = 1100 b the output signal reflects the loss of signal status ss readable in frs0.los ipu general purpose input (gpi) pc(1:4).rpc(3:0) = 1001 b the digital signal level applied externally can be read through a status register. for unused rpax pins this configuration is recommended. o general purpose output high (gpoh) pc(1:4).rpc(3:0) = 1010 b a fixed high output level is driven. o general purpose output low (gpol) pc(1:4).rpc(3:0) = 1011 b a fixed low output level is driven. 56 (d8) xdi i transmit data input transmit data received from the system highway. latching of data is done with rising or falling transitions of sclkx according to bit sic3.resx. the delay between the beginning of time slot 0 and the initial edge of sclkx (after sypx goes active) is determined by the registers xc(1:0). at higher data rates (> 1.544/2.048 mbit/s) sampling of data is defined by bits sic2.sics(2:0). 64 (c6) sclkx i pu transmit system clock working clock for the transmit system interface with a frequency of 16.384/8.192/4.096/2.048 in e1 mode and 16.384/8.192/4.096/2.048 mhz (sic2.ssc2 = 0) or 12.352/6.176/3.088/1.544 mhz (sic2.ssc2 = 1) in t1/j1 mode. table 4 pin definitions - system interface (cont?d) pin or ball no. name pin type buffer type function falc ? 56 pef 2256 h/e external signals user?s manual 43 ds1.1, 2003-10-23 hardware description 60 (b8) 61 (a9) 62 (a8) 63 (b7) xpa xpb xbc xpd transmit multifunction ports depending on programming of bits pc(1:4).xpc(3:0) these multifunction ports carry information to the system interface or from the system to the falc ? 56. after reset the ports are configured to be inputs. with the selection of the appropriate pin function, the corresponding input/output configuration is achieved automatically. depending on bit sic3.resx latching/transmission of data is done with the rising or falling edge of sclkx. if not connected, an internal pullup transistor ensures a high input level. each input function (sypx , xmfs, xsig or tclk) may only be selected once. sypx and xmfs must not be used in parallel. selectable pin functions are described below. ipu synchronous pulse transmit (sypx ) pc(1:4).xpc(3:0) = 0000 b together with the values of registers xc(0:1) this signal defines the beginning of time slot 0 at system highway port xdi . the pulse cycle is an integer multiple of 125 s. sypx must not be used in parallel with xmfs. ipu transmit multiframe synchronization (xmfs) pc(1:4).xpc(3:0) = 0001 b this port defines the frame and multiframe begin on the transmit system interface ports xdi and xsig. depending on pc5.cxmfs the signal on xmfs is active high or low. xmfs must not be used in parallel with sypx . note: a new multiframe position has settled at least one multiframe after pulse xmfs has been supplied. table 4 pin definitions - system interface (cont?d) pin or ball no. name pin type buffer type function falc ? 56 pef 2256 h/e external signals user?s manual 44 ds1.1, 2003-10-23 hardware description 60 (b8) 61 (a9) 62 (a8) 63 (b7) xpa xpb xbc xpd ipu transmit signaling data (xsig) pc(1:4).xpc(3:0) = 0010 b input for transmit signaling data received from the signaling highway. optionally, (sic3.ttrf = 1), sampling of xsig data is controlled by the active high xsigm marker. at higher data rates sampling of data is defined by bits sic2.sics(2:0). ipu transmit clock (tclk) pc(1:4).xpc(3:0) = 0011 b a 2.048/8.192-mhz (e1) or 1.544/6.176-mhz (t1/j1) clock has to be sourced by the system if the internally generated transmit clock (generated by dco-x) shall not be used. optionally this input is used as a synchronization clock for the dco-x circuitry with a frequency of 2.048 (e1) or 1.544 mhz (t1/j1). o transmit multiframe begin (xmfb) pc(1:4).xpc(3:0) = 0100 b xmfb marks the beginning of every transmitted multiframe on xdi. the signal is active high for one 2.048 (e1) or 1.544 mhz (t1/j1) period. o transmit signaling marker (xsigm) pc(1:4).xpc(3:0) = 0101 b e1: marks the transmit time slots on xdi of every frame which are defined by register ttr(1:4). t1/j1: marks the transmit time slots on xdi of every frame which are defined by register ttr(1:4) (if not cas-br is used). when using the cas-br signaling scheme the robbed bit of each channel in every sixth frame is marked. table 4 pin definitions - system interface (cont?d) pin or ball no. name pin type buffer type function falc ? 56 pef 2256 h/e external signals user?s manual 45 ds1.1, 2003-10-23 hardware description 60 (b8) 61 (a9) 62 (a8) 63 (b7) xpa xpb xbc xpd o data link bit transmit (dlx) pc(1:4).xpc(3:0) = 0110 b e1: marks the s a (8:4)-bits within the data stream on xdi. the s a (8:4)-bit positions in time slot 0 of every frame not containing the frame alignment signal are selected by register xc0.sa8e to xc0.sa4e. t1/j1: this output provides a 4-khz signal which marks the dl-bit position within the data stream on xdi (in esf mode only). o transmit clock (xclk) pc(1:4).xpc(3:0) = 0111 b transmit line clock of 2.048 mhz (e1) or 1.544 mhz (t1/j1) derived from sclkx/r, rclk or generated internally by dco circuitries. ipu transmit line tristate (xlt) pc(1:4).xpc(3:0) = 1000 b a high level on this port sets the transmit lines xl1/2 or xdop/n into tristate mode. this pin function is logically ored with register bit xpm2.xlt. ipu general purpose input (gpi) pc(1:4).xpc(3:0) = 1001 b the digital signal level applied externally can be read through a status register. for unused xpax pins this configuration is recommended. o general purpose output high (gpoh) pc(1:4).xpc(3:0) = 1010 b a fixed high output level is driven. o general purpose output low (gpol) pc(1:4).xpc(3:0) = 1011 b a fixed low output level is driven. table 4 pin definitions - system interface (cont?d) pin or ball no. name pin type buffer type function falc ? 56 pef 2256 h/e external signals user?s manual 46 ds1.1, 2003-10-23 hardware description table 5 miscellaneous pin definitions pin (ball) no. name pin type buffer type function power supply 80 (b2) vsel i pu voltage selection for digital core selects between single and dual power supply mode. 0 b vsel_0 , dual power supply mode, vddc must be supplied with 1.8 v while al other power supplies require 3.3 v. 1 b vsel_1 , single power supply mode, all power supply voltages are 3.3 v. note: dual power supply mode is recommended for lowest power dissipation. 4 (d3) v ddr s positive power supply - analog receiver 3.3 v 5% 6 (d2) v ddx s positive power supply - analog transmitter 3.3 v 5% 9 (e2) v ddp s power supply - system pll 3.3 v 5% 74 (a4) v ddc s power supply - digital core connected to a 1.8-v 10% power supply in dual supply mode. attention: this pin must not be used to supply external devices. 9 (a5) v dd s positive power supply - digital pads 3.3 v 5% 24 (c8) 34 (e2) 41 (g4) 58 (j6) 71 (j9) falc ? 56 pef 2256 h/e external signals user?s manual 47 ds1.1, 2003-10-23 hardware description 1 (a1) v ss s ground all analog and digital circuits are connected to a common ground within the device package. 8 (d1) 10 (e4) 10 (b9) 25 (c5) 35 (e4) 42 (h9) 59 (j3) 72 (j7) analog switch 19 (h1) as1 i/o analog analog switch these pins provide the terminals for an analog switch to be used in redundancy applications. 20 (h2) as2 i/o analog device reset 13 (f3) res i hardware reset during reset the falc ? 56 needs an active clock on pin mclk. during reset all bidirectional output stages are in input mode, if signal rd is ?high? (which disables the data bus d(15:0) output drivers). 0 b res_0 , device reset. 1 b res_1 , operational mode. jtag test interface 14 (f1) trs ipu test access port (tap) reset initializes the boundary scan test logic. if the boundary scan logic is not used, this pin must be connected to rst or vss 0 b trs_0 , tap controller reset. 1 b trs_1 , tap operational mode. 15 (g1) tdi ipu test data input boundary scan input signal. 16 (f2) tms ipu test mode select boundary scan test mode select. table 5 miscellaneous pin definitions (cont?d) pin (ball) no. name pin type buffer type function falc ? 56 pef 2256 h/e external signals user?s manual 48 ds1.1, 2003-10-23 hardware description note: od = open drain output pp = push/pull output pu = input or input/output comprising an internal pullup device to override the internal pullup by an external pulldown, a resistor value of 22 k ? is recommended. the pullup devices are activated during reset, this means their state is undefined until the reset signal has been applied. unused input pins containing pullups can be left open. unused input pins without pullups shall be connected to v dd or v ss level to prevent floating. unused output pins shall be left open. 17 (g3) tck ipu test clock boundary scan test clock. 18 (g2) tdo o test data output boundary scan output signal. unused pins - (e5) n.c. reserved this ball is not connected within the p-lbga-81-1 package but should be left open for compatibility with future products. there are no unused pins in the p-mqfp-80-1 package. table 5 miscellaneous pin definitions (cont?d) pin (ball) no. name pin type buffer type function falc ? 56 pef 2256 h/e functional description e1/t1/j1 user?s manual 49 ds1.1, 2003-10-23 hardware description 3 functional descr iption e1/t1/j1 3.1 functional overview the falc ? 56 device contains analog and digital function blocks that are configured and controlled by an external microprocessor or microcontroller. the functional block diagram is shown in figure 5 . the main interfaces are receive and transmit line interface pcm system highway interface/h.100 bus microprocessor interface boundary scan interface as well as several control lines for reset and clocking purpose. the main internal functional blocks are analog line receiver with equalizer network and clock/data recovery analog line driver with programmable pulse shaper and line build out central clock generation module elastic buffers for receive and transmit direction receive framer, receive line decoding, alarm detection, prbs and performance monitoring transmit framer, receive line encoding, alarm and prbs generation receive jitter attenuator transmit jitter attenuator three hdlc controllers (one of them including ss7 and bom support) and cas signaling controller test functions (loop switching local - remote - payload - single channel) register access interface boundary scan control falc ? 56 pef 2256 h/e functional description e1/t1/j1 user?s manual 50 ds1.1, 2003-10-23 hardware description 3.2 block diagram figure 5 block diagram f56v2_block_diagra m jtag boundary scan ieee 1149 clocking unit microprocessor interface intel/motorola receive jitter attenuator transmit jitter attenuator long & short haul receive line interface clock & data recovery long & short haul line transmit interface receive framer alarm detector prbs monitor line decoder pe r f o r m. mo n i t o r receive ela st ic bu f f er transmit ela st ic bu f f er frame generator alarm generator prbs generator line coding signaling controller hdlc/bom/ss7 signaling controller cas-cc cas-br receive syst e m interface transmit syst e m interface trs tdi tms tck tdo d(15:0) a(7:0) cs wr/rw rd/ds al e bhe/ bl e im res int mclk sy nc se c/ fs c clk1 clk2 rclk tclk scl kx xpd xpc xpb xpa xdi rpd rpc rpb rpa rdo dbw scl kr rl1 rdip roid rl2 rdin rclki xl2 xdon xfm xl1 xdop xoi d re m ot e l o op + jat t local loop payload loop rclk scl kr falc ? 56 pef 2256 h/e functional description e1/t1/j1 user?s manual 51 ds1.1, 2003-10-23 hardware description 3.3 functional blocks 3.3.1 microprocessor interface the communication between the cpu and the falc ? 56 is done using a set of directly accessible registers. the interface can be configured as intel or motorola type with a selectable data bus width of 8 or 16 bits. the cpu transfers hdlc data to and from the falc ? 56 (through 64-byte deep fifos per direction), sets the operating modes, controls function sequences, and gets status information by writing or reading control and status registers. all accesses can be done as byte or word accesses if enabled. if 16-bit bus width is selected, access to lower/upper part of the data bus is determined by address line a0 and signal bhe /ble as shown in table 6 and table 7 . table 8 shows how the ale ( a ddress l atch e nable) line is used to control the bus structure and interface type. the switching of ale allows the falc ? 56 to be directly connected to a multiplexed address/data bus. 3.3.1.1 mixed byte/word access to the fifos reading from or writing to the internal fifos (rfifo and xfifo) can be done using a 8-bit (byte) or 16-bit (word) access depending on the selected bus interface mode. randomly mixed byte/word access to the fifos is allowed without any restrictions. table 6 data bus access (16-bit intel mode) bhe a0 register access falc ? 56 data pins used 0 0 fifo word access register word access (even addresses) d(15:0) 0 1 register byte access (odd addresses) d(15:8) 1 0 register byte access (even addresses) d(7:0) 1 1 no transfer performed none table 7 data bus access (16-bit motorola mode) ble a0 register access falc ? 56 data pins used 0 0 fifo word access register word access (even addresses) d(15:0) 0 1 register byte access (odd addresses) d(7:0) 1 0 register byte access (even addresses) d(15:8) 1 1 no transfer performed none falc ? 56 pef 2256 h/e functional description e1/t1/j1 user?s manual 52 ds1.1, 2003-10-23 hardware description the assignment of registers with even/odd addresses to the data lines in case of 16-bit register access depends on the selected microprocessor interface mode: intel (address n + 1) (address n) motorola (address n) (address n + 1) n: even address 3.3.1.2 fifo structure in transmit and receive direction of the signaling controller 64-byte deep fifos are provided for the intermediate storage of data between the system internal highway and the cpu interface. the fifos are divided into two halves of 32 bytes. only one half is accessible to the cpu at any time. in case 16-bit data bus width is selected by fixing pin dbw to logical 1 word access to the fifos is enabled. data output to bus lines d(15:0) as a function of the selected interface mode is shown in figure 6 and figure 7 . of course, byte access is also allowed. the effective length of the accessible part of rfifo can be changed from 32 bytes (reset value) down to 2 bytes. table 8 selectable bus and microprocessor interface configuration ale im microprocessor interface bus structure v ss /v dd 1 motorola de-multiplexed v ss /v dd 0 intel de-multiplexed switching 0 intel multiplexed data lines d15 d8 d7 d0 falc ? 56 pef 2256 h/e functional description e1/t1/j1 user?s manual 53 ds1.1, 2003-10-23 hardware description figure 6 fifo word access (intel mode) figure 7 fifo word access (motorola mode) byte 4 byte 1 byte 2 byte 3 d15 d8 d7 d0 rfifo 1 2 3 4 32 1 32 byte 4 byte 1 byte 2 byte 3 d15 d8 d7 d0 xfifo 1 2 3 4 32 1 32 byte 32 byte 32 f0112 byte 4 byte 1 byte 2 byte 3 d15 d8 d7 d0 rfifo 1 2 3 4 32 1 32 byte 4 byte 1 byte 2 byte 3 d15 d8 d7 d0 xfifo 1 2 3 4 32 1 32 byte 32 byte 32 f0113 falc ? 56 pef 2256 h/e functional description e1/t1/j1 user?s manual 54 ds1.1, 2003-10-23 hardware description 3.3.1.3 interrupt interface special events in the falc ? 56 are indicated by means of a single interrupt output with programmable characteristics (open drain or push-pull, defined by register ipc), which requests the cpu to read status information from the falc ? 56, or to transfer data from/to the falc ? 56. since only one int request output is provided, the cause of an interrupt must be determined by the cpu by reading the falc ? 56?s interrupt status registers (gis, isr(5:0)). the interrupt on pin int and the interrupt status bits are reset by reading the interrupt status registers. register isr(5:0) are of type ?clear on read?. the structure of the interrupt status registers is shown in figure 8 . figure 8 interrupt status registers each interrupt indication of registers isr(5: 0) can be selectively masked by setting the according bit in the corresponding mask registers imr(5:0). if the interrupt status bits are masked they neither generate an interrupt at int nor are they visible in isr(5:0). gis, the non-maskable global interrupt status register, serves as pointer to pending interrupts. after the falc ? 56 has requested an interrupt by activating its int pin, the cpu should first read the global interrupt status register gis to identify the requesting imr0 f0127 v1.0 global interrupt status register gis isr0 isr0 isr1 isr2 isr3 isr4 isr5 imr1 isr1 imr2 isr2 imr3 isr3 imr4 isr4 imr5 isr5 falc ? 56 pef 2256 h/e functional description e1/t1/j1 user?s manual 55 ds1.1, 2003-10-23 hardware description interrupt source register. after reading the assigned interrupt status registers isr(5:0), the pointer in register gis is cleared or updated if another interrupt requires service. if all pending interrupts are acknowledged by reading (gis is reset), pin int goes inactive. updating of interrupt status registers isr(5:0) and gis is only prohibited during read access. masked interrupts visible in status registers each interrupt source can be individually masked to prevent an interrupt to be generated. only unmasked interrupts trigger the interrupt line and are visible in their interrupt status register. the global interrupt status register (gis) indicates those interrupt status registers with active interrupt indications (gis.isr(5:0)). an additional mode can be selected via bit gcr.vis. in this mode, masked interrupt status bits neither generate an interrupt on pin int nor are they visible in gis, but are displayed in the corresponding interrupt status register(s) isr(5:0). this mode is useful when some interrupt status bits are to be polled in the individual interrupt status registers. note: in the visible mode, all active interrupt status bits, whether the corresponding actual interrupt is masked or not, are reset when the interrupt status register is read. thus, when polling of some interrupt status bits is desired, care must be taken that unmasked interrupts are not lost in the process. all unmasked interrupt statuses are treated as before. please note that whenever polling is used, all interrupt status registers concerned have to be polled individually (no ?hierarchical? polling possible), since gis only contains information on actually generated, which means unmasked interrupts. falc ? 56 pef 2256 h/e functional description e1/t1/j1 user?s manual 56 ds1.1, 2003-10-23 hardware description 3.3.2 boundary scan interface in the falc ? 56 a t est a ccess p ort (tap) controller is implemented. the essential part of the tap is a finite state machine (16 states) controlling the different operational modes of the boundary scan. both, tap controller and boundary scan, meet the requirements given by the jtag standard ieee 1149.1. figure 9 gives an overview. figure 9 block diagram of test access port and boundary scan after switching on the device (power-on), a reset signal has to be applied to trs , which forces the tap controller into test logic reset state. for normal operation without boundary scan access, the boundary reset pin trs can be tied to the device reset pin res . if no boundary scan operation is used, trs has to be connected to rst or v ss . tms, tck and tdi do not need to be connected since pullup transistors ensure high input levels in this case. f0115 trs tck tms tdi tdo clock test control data in enable data out clock generation reset tap controller finite state machine instruction register test signal generator tap controller reset identification register (32 bits) control bus boundary scan (n bits) 1 2 n bd data in bd data out id data out falc ? 56 pef 2256 h/e functional description e1/t1/j1 user?s manual 57 ds1.1, 2003-10-23 hardware description test handling (boundary scan operation) is performed using the pins tck (test clock), tms (test mode select), tdi (test data input) and tdo (test data output) when the tap controller is not in its reset state, that means trs is connected to v dd or it remains unconnected due to its internal pull up. test data at tdi is loaded with a clock signal connected to tck. "1" or "0" on tms causes a transition from one controller state to another; constant "1" on tms leads to normal operation of the chip. the state machine is shown in figure 10 . an input pin (i) uses one boundary scan cell (data in), an output pin (o) uses two cells (data out and enable) and an i/o-pin (i/o) uses three cells (data in, data out and enable). note that most functional output and input pins of the falc ? 56 are tested as i/o pins in boundary scan, hence using three cells. the desired test mode is selected by serially loading a 8-bit instruction code into the instruction register through tdi (lsb first). extest is used to examine the interconnection of the devices on the board. in this test mode at first all input pins capture the current level on the corresponding external interconnection line, whereas all output pins are held at constant values ("0" or "1"). then the contents of the boundary scan is shifted to tdo. at the same time the next scan vector is loaded from tdi. subsequently all output pins are updated according to the new boundary scan contents and all input pins again capture the current external level afterwards, and so on. sample is a test mode which provides a snapshot of pin levels during normal operation. idcode : a 32-bit identification register is serially read out on pin tdo. it contains the version number (4 bits), the device code (16 bits) and the manufacturer code (11 bits). the lsb is fixed to "1". the id code field is set to: 0001 0000 0000 1011 1110 0000 1000 0011 version = 3 h, part number = 00be h , manufacturer = 083 h (including lsb, fixed to "1") bypass : a bit entering tdi is shifted to tdo after one tck clock cycle. an alphabetical overview of all tap controller operation codes is given in table 9 . table 9 tap controller instruction codes tap instruction instruction code bypass 11111111 extest 00000000 idcode 00000100 sample 00000001 reserved for device test 01010011 falc ? 56 pef 2256 h/e functional description e1/t1/j1 user?s manual 58 ds1.1, 2003-10-23 hardware description figure 10 jtag tap controller state machine f56v2_jtag_state_machin e reset test logic run test/idle select dr scan capture data to dr shift dr exit1 dr pause dr exit2 dr update dr select ir scan capture data to ir shift ir exit1 ir pause ir exit2 ir update ir 1 0 1 1 tms = 1 0 0 0 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 1 1 0 11 0 falc ? 56 pef 2256 h/e functional description e1/t1/j1 user?s manual 59 ds1.1, 2003-10-23 hardware description 3.3.3 master clocking unit the falc ? 56 provides a flexible clocking unit, which references to any clock in the range of 1.02 to 20 mhz supplied on pin mclk. the clocking unit has to be tuned to the selected reference frequency by setting the global clock mode registers gcm(8:1) accordingly. the calculation formulas for the appropriate register settings can be found in chapter 9.2 on page 227 or chapter 10.2 on page 348 . a calculation tool is available to evaluate the required register settings automatically (see chapter 13.3 on page 501 ). all required clocks for e1 or t1/j1 operation are generated by this circuit internally. the global setting depends only on the selected master clock frequency and is the same for e1 and t1/j1 because both clock rates are provided simultaneously. to meet the e1 requirements the mclk reference clock must have an accuracy of better than 32 ppm. the synthesized clock can be controlled on pins clk1, clk2, rclk, sclkr and xclk. . figure 11 flexible master clock unit f56v2_clocking_1 flexible master clock unit mclk e1 clocks t1/j1 clocks gcm1...gcm8 falc ? 56 pef 2256 h/e functional description e1/t1/j1 user?s manual 60 ds1.1, 2003-10-23 hardware description 3.4 power supply 3.4.1 power supply configuration the falc ? 56 uses two different supply voltages internally, which are 3.3 v and 1.8 v. for compatibility reasons, it is possible to operate the device off a single 3.3 v power supply. in this operation mode, the 1.8-v core voltage is generated internally using an on-chip voltage regulator. in order to minimize the power consumption it is also possible to operate the device using separate external 3.3-v and 1.8-v supplies. suppl y voltage selection is done by using control pin vsel (voltage select). see figure 11 and figure 12 for more detail. note: the 1.8 v power supply requires de-coupling in either operation mode. the voltage levels of v dd , v ddp , v ddx , and v ddr must always be above the v ddc level, even during device power-up and power-down. otherwise cross currents through esd protection diodes will occur. figure 12 single voltage power supply mode f56v2_power_supply_singl e v ddp v ddx v ddr v ssp v ssx v ssr v ddc vsel falc ? 56 (can be left open) 3.3 v v dd 3.3 v v ss falc ? 56 pef 2256 h/e functional description e1/t1/j1 user?s manual 61 ds1.1, 2003-10-23 hardware description figure 13 dual voltage power supply mode 3.4.2 power supply de-coupling to gain best performance, the following values are recommended for the external de-coupling between v ddc and v ss . table 10 decoupling capacitor parameters parameter value capacitance (c dec ) 470 nf 20 %, alternatively: 2 220 nf 20 % capacitor material ceramic, type x7r or compatible esr < 30 m ? loop inductance (l l ) between v ddc , capacitor and next v ss pin < 10 nh f56v2_power_supply_du a v ddx v ddr v ddp v ddc 3.3 v 1.8 v v ssp v ssx v ssr vsel falc ? 56 v dd v ss falc ? 56 pef 2256 h/e functional description e1/t1/j1 user?s manual 62 ds1.1, 2003-10-23 hardware description figure 14 decoupling capacitor placement f56v2_power_supply_decouplin g v ddc l l v ss c dec falc ? 56 pef 2256 h/e functional description e1 user?s manual 63 ds1.1, 2003-10-23 hardware description 4 functional description e1 4.1 receive path in e1 mode figure 15 receive clock system (e1) 4.1.1 receive line interface for data input, three different data types are supported: ternary coded signals received at multif unction ports rl1 and rl2 from a ternary interface. the ternary interface is selected if lim1.drs is reset. digital dual-rail signals received on ports rdip and rdin. the dual-rail interface is selected if lim1.drs and fmr0.rc1 is set. unipolar data on port roid received from a fiber-optical interface. the optical interface is selected if lim1.drs is set and fmr0.rc1 is reset. 4.1.2 receive short and long-haul interface the falc ? 56 has an integrated short-haul and long-haul line interface, including a receive equalization network and noise filtering. the line interface automatically adapts equalizer clock & data recovery dpll li ne decoder alarm detector analog los detector rdata rclk sync rl1/rdip/roid rl2/rdin/rclki dco-r receive jitter attenuator mc lk fsc receive system interface f0117 falc ? 56 pef 2256 h/e functional description e1 user?s manual 64 ds1.1, 2003-10-23 hardware description to the received signal amplitude, no selection of long haul or short haul mode is necessary. 4.1.3 receive equalization network (e1) the falc ? 56 automatically recovers the signals received on pins rl1/2 in a range of up to -43 db. the maximum reachable length with a 22 awg twisted pair cable is 1500 m. the integrated receive equalization network recovers signals with up to -43 db of cable attenuation. noise filters eliminate the higher frequency part of the received signals. the incoming data is peak-detected and sliced to produce the digital data stream. the slicing level is software selectable in four steps (45%, 50%, 55%, 67%). for typical e1 applications, a level of 50% is used. the received data is then forwarded to the clock & data recovery unit. the receive equalizer characteristic is programmable, for example to enable the use of non-standard cable types or to adapt to specific receive conditions. 4.1.4 receive line attenuation indication (e1) status register res reports the current receive line attenuation in a range from 0 to -43 db in 25 steps of approximately 1.7 db each. the least significant 5 bits of this register indicate the cable attenuation in db. these 5 bits are only valid in combination with the most significant two bits (res.ev1/0 = 01). 4.1.5 receive clock and data recovery (e1) the analog received signal on port rl1/2 is equalized and then peak-detected to produce a digital signal. the digital received signal on port rdip/n is directly forwarded to the dpll. the receive clock and data recovery extracts the route clock from the data stream received at the rl1/2, rdip/rdin or roid lines and converts the data stream into a single-rail, unipolar bit stream. the clock and data recovery uses an internally generated high frequency clock based on mclk. the recovered route clock or a de-jittered clock can be output on pin rclk as shown in table 11 . see also table 14 on page 71 for details of master/slave clocking. falc ? 56 pef 2256 h/e functional description e1 user?s manual 65 ds1.1, 2003-10-23 hardware description the intrinsic jitter generated in the absence of any input jitter is not more than 0.035 ui. in digital bipolar line interface mode the clock and data recovery requires hdb3 coded signals with 50% duty cycle. 4.1.6 receive line coding (e1) the hdb3 line code or the ami coding is provided for the data received from the ternary or the dual rail interface. all code violations that do not correspond to zero substitution rules are detected. if a bit error causes a code violation that leads to a valid substitution pattern, this code violation is not detected and the substitution pattern is replaced by the corresponding zero pattern. the detected errors increment the 16-bit code violation counter. in case of the optical interface a selection between the nrz code and the cmi code (1t2b) with hdb3 or ami postprocessing is provided. if cmi code is selected the receive route clock is recovered from the data stream. the cmi decoder does not correct any errors. in case of nrz coding data is latched with the falling edge of signal rclki. the hdb3 code is used along with double violation detection or extended code violation detection (selectable by fmr0.exze)). in ami code all code violations are detected. the detected errors increment the 16-bit code violation counter. when using the optical interface with nrz coding, the decoder is bypassed and no code violations are detected. table 11 rclk output selection (e1) clock source rclk frequency cmr1. dcs cmr1. rs1/0 receive data (2.048 mbit/s on rl1/rl2, rdip/rdin or roid) 2.048 mhz (recovered clock) 00 receive data in case of los constant high 0 01 2.048 mhz (generated by dco-r, synchronized on sync) 110 dco-r 2.048 mhz 10 8.192 mhz 11 falc ? 56 pef 2256 h/e functional description e1 user?s manual 66 ds1.1, 2003-10-23 hardware description 4.1.7 receive line termination (e1) the signal at the ternary interface is received at both ends of a transformer. a termination resistor is used to achieve line impedance matching (see figure 16 and table 12 ). the e1 operating modes 75 ? or 120 ? are selectable by switching an internal termination resistor of 300 ? (see lim0.rtrs) in parallel. this selection does not require the change of transformers. figure 16 receiver configuration (e1) 4.1.8 receive line monitoring mode for short-haul applications like shown in figure 17 , the receive equalizer can be switched into receive line monitoring mode (lim0.rlm = 1). one device is used as a short-haul receiver while the other is used as a short-haul monitor. in this mode the receiver sensitivity is increased to detect an incoming signal of -20 db resistive attenuation. the required resistor values are given in table 13 . table 12 recommended receiver configuration values (e1) line impedance external resistor r 2 internal resistor r1 transformer ratio t 2 :t 1 120 ? 120 ? 1)2) 1) this includes all parasitic effects caused by circuit board design. 2) can be set to 100 ? for common e1/t1 applications. off (lim0.rtrs = 0 b )1 : 1 75 ? 75 ? 1) off (lim0.rtrs = 0 b )1 : 1 120 ? 1) 2) on (lim0.rtrs = 1 b )1 : 1 f56v2_receiver_1 rl1 rl2 r 2 r int line t 2 t 1 falc ? 56 pef 2256 h/e functional description e1 user?s manual 67 ds1.1, 2003-10-23 hardware description figure 17 receive line monitoring (e1) using the receive line monitor mode and the hardware tristate function of transmit lines xl1/2, the falc ? 56 now supports applications connecting two devices to one receive and transmission line. in these kind of applications both devices are working in parallel for redundancy purpose (see figure 18 ). while one of them is driving the line, the other one must be switched into transmit line tristate mode. if both channels are configured identically and supplied with the same system data and clocks, the transmit path can be switched from one channel to the other without causing a synchronization loss at the remote end. due to the use of the receive line monitor mode, this setup is limited to short table 13 external component recommendations (monitoring) parameter 1) 1) this includes all parasitic effects caused by circuit board design. lim0.rtrs characteristic impedance 75 ? 120 ? r 1 0 b 75 ? 1 % 120 ? 1 % 1 b 120 ? 1 % - r 2 0 b 75 ? 1 % 120 ? 1 % 1 b 120 ? 1 % - r 3 x b 330 ? 1 % 510 ? 1 % t 2 : t 1 1 : 1 1 : 1 f56v2_receiver_ 4 receiver monitor rl1 e1/t1/j1 receive line lim0.rlm=0 lim0.rlm=1 r1 r2 r3 r3 rl2 rl1 rl2 t2 : t1 t2 : t1 resistive - 20 db network falc ? 56 pef 2256 h/e functional description e1 user?s manual 68 ds1.1, 2003-10-23 hardware description haul applications. switching between both devices can be done through the microcontroller interface or by using the tristate hardware input pin as shown in the figure. figure 18 short haul protection switching application (e1) for long haul redundancy requirements (see figure 19 ), the analog switches can be used to enable the line termination for the active device and to disable it for the stand-by part. switching between both devices is controled through the microcontroller interface. f56v2_receiver_2 e1/t1/j1 receive line rl1 rl2 rdo rl1 rl2 rdo xl1 xl2 e1/t1/j1 transmit line xdi xl1 xl2 xdi trist trist 1 active device stand-by device falc ? 56 pef 2256 h/e functional description e1 user?s manual 69 ds1.1, 2003-10-23 hardware description figure 19 long haul protection switching application (e1) 4.1.9 loss-of-signal detection (e1) there are different definitions for detecting loss-of-signal (los) alarms in the itu-t g.775 and ets 300233. the falc ? 56 covers all these standards. the los indication is performed by generating an interrupt (if not masked) and activating a status bit. additionally a los status change interrupt is programmable by using register gcr.sci. detection: an alarm is generated if the incoming data stream has no pulses (no transitions) for a certain number (n) of consecutive pulse periods. ?no pulse? in the digital receive interface means a logical zero on pins rdip/rdin/roid. a pulse with an amplitude less than q db below nominal is the criteria for ?no pulse? in the analog receive interface (lim1.drs = 0). the receive signal level q is programmable by three f56v2_receiver_ 3 e1/t1/j1 receive line rl1 rl2 rdo rl1 rl2 rdo xl1 xl2 e1/t1/j1 transmit line xdi xl1 xl2 xdi active device stand-by device falc ? 56 pef 2256 h/e functional description e1 user?s manual 70 ds1.1, 2003-10-23 hardware description control bits lim1.ril(2:0) (see chapter 11.3 on page 466 ). the number n can be set by an 8-bit register (pcd). the contents of the pcd register is multiplied by 16, which results in the number of pulse periods, i.e. the time which has to suspend until the alarm has to be detected. the programmable range is 16 to 4096 pulse periods. ets300233 requires detection intervals of at least 1 ms. this time period results always in a lfa (loss of frame alignment) before a los is detected. recovery: in general the recovery procedure starts after detecting a logical one (digital receive interface) or a pulse (analog receive interface) with an amplitude more than q db (defined by lim1.ril(2:0)) of the nominal pulse. the value in the 8-bit register pcr defines the number of pulses (1 to 255) to clear the los alarm. if a loss-of-signal condition is detected, the data stream can optionally be cleared automatically to avoid bit errors before los is indicated. the selection is done by lim1.clos = 1. 4.1.10 receive jitter attenuator (e1) the receive jitter attenuator is placed in the receive path. the working clock is an internally generated high frequency clock based on the clock provided on pin mclk. the jitter attenuator meets the requirements of itu-t i.431, g. 736 to 739, g.823 and etsi tbr12/13. the internal pll circuitry dco-r generates a "jitter-free" output clock which is directly dependent on the phase difference of the incoming clock and the jitter attenuated clock.the receive jitter attenuator can be synchronized either on the extracted receive clock rclk or on a 2.048-mhz/8-khz clock provided on pin sync (8 khz in master mode only). the received data is written into the receive elastic buffer with rclk and are read out with the de-jittered clock sourced by dco-r. the jitter attenuated clock can be output on pins rclk, clk1 or sclkr. optionally an 8-khz clock is provided on pin sec/fsc. the dco-r circuitry attenuates the incoming jittered clock starting at 2-hz jitter frequency with 20 db per decade fall-off. wander with a jitter frequency below 2 hz is bypassed unattenuatedly. the intrinsic jitter in the absence of any input jitter is < 0.02 ui. for some applications it might be useful to start jitter attenuation at lower frequencies. therefore the corner frequency is switchable by the factor of ten down to 0.2 hz (lim2.scf). the dco-r circuitry is automatically centered to the nominal bit rate if the reference clock on pin sync/rclk is missed for 2, 3 or 4 of the 2.048-mhz clock periods. this center function of dco-r can be disabled (cmr2.dcf = 1) in order to accept a gapped reference clock. in analog line interface mode rclk is always running. only in digital line interface mode with single-rail data a gapped clock can occur. the receive jitter attenuator works in two different modes: falc ? 56 pef 2256 h/e functional description e1 user?s manual 71 ds1.1, 2003-10-23 hardware description slave mode in slave mode (lim0.mas = 0) the dco-r is synchronized with the recovered route clock. in case of los the dco-r switches automatically to master mode. if bit cmr1.dcs is set automatic switching from rclk to sync is disabled. master mode in master mode (lim0.mas = 1) the jitter attenuator is in free running mode if no clock is supplied on pin sync. if an external clock on the sync input is applied, the dco-r synchronizes to this input. the external frequency can be 2.048 mhz (ipc.ssyf = 0) or 8.0 khz (ipc.ssyf = 1). the following table shows the clock modes with the corresponding synchronization sources. the jitter attenuator meets the jitter transfer requirements of the itu-t i.431 and g.735 to 739 (refer to figure 20 ) table 14 system clocking (e1) mode internal los active sync input system clocks generated by dco-r master independent fixed to v dd dco-r centered, if cmr2.dcf = 0. (cmr2.dcf should not be set) master independent 2.048 mhz synchronized to sync input (external 2.048 mhz, ipc.ssyf = 0) master independent 8.0 khz synchronized to sync input (external 8.0 khz, ipc.ssyf = 1, cmr2.dcf = 0) slave no fixed to v dd synchronized to line rclk slave no 2.048 mhz synchronized to line rclk slave yes fixed to v dd cmr1.dcs = 0: dco-r is centered, if cmr2.dcf = 0. (cmr2.dcf should not be set) cmr1.dcs = 1: synchronized on line rclk slave yes 2.048 mhz cmr1.dcs = 0: synchronized to sync input (external 2.048 mhz) cmr1.dcs = 1: synchronized on line clock rclk falc ? 56 pef 2256 h/e functional description e1 user?s manual 72 ds1.1, 2003-10-23 hardware description . figure 20 jitter attenuation performance (e1) also the requirements of etsi tbr 12/13 are satisfied. insuring adequate margin against tbr 12/13 output jitter limit with 15 ui input at 20 hz the dco-r circuitry starts jitter attenuation at about 2 hz. itd10312 1 -60 frequency attenuation 10 100 1000 10000 100000 hz itu g.736 template -50 -40 -30 -20 -10 0 10 db falc r falc ? 56 pef 2256 h/e functional description e1 user?s manual 73 ds1.1, 2003-10-23 hardware description 4.1.11 jitter tolerance (e1) the falc ? 56 receiver?s tolerance to input jitter complies with itu requirements. figure 21 shows the curves of different input jitter specifications stated below as well as the falc ? 56 performance. figure 21 jitter tolerance (e1) 4.1.12 output jitter (e1) in the absence of any input jitter the falc ? 56 generates the output jitter which is specified in the table 15 below. table 15 output jitter (e1) specification measurement filter bandwidth output jitter (ui peak to peak) lower cutoff upper cutoff itu-t i.431 20 hz 100 khz < 0.015 700 hz 100 khz < 0.015 etsi tbr 12 40 hz 100 khz < 0.11 jitter amplitude jitter frequency 1 10 100 1000 10000 100000 hz ui 1 0.1 10 100 1000 pub 62411 tr-nwt 000499 cat ii ccitt g.823 itu-t i.431 falc ? f0025 falc ? 56 pef 2256 h/e functional description e1 user?s manual 74 ds1.1, 2003-10-23 hardware description 4.1.13 framer/synchronizer (e1) the following functions are performed: synchronization on pulse frame and multiframe error indication when synchronization is lost. in this case, ais is sent automatically to the system side and remote alarm is sent to the remote end if enabled. initiating and controlling of resynchronization after reaching the asynchronous state. this can be done automatically by the falc ? 56 or user controlled using the microprocessor interface. detection of remote alarm indication from the incoming data stream. separation of service bits and data link bits. this information is stored in status registers. generation of various maskable interrupt statuses of the receiver functions. generation of control signals to synchronize the crc checker, and the receive elastic buffer. if programmed and applicable to the selected multiframe format, crc checking of the incoming data stream is done by generating check bits for a crc submultiframe according to the crc4 procedure (as defined in itu-t g.704). these bits are compared with those check bits that are received during the next crc submultiframe. if there is at least one mismatch, the 16-bit crc error counter is incremented. 4.1.14 receive elastic buffer (e1) the received bit stream is stored in the receive elastic buffer. the memory is organized as a two-frame elastic buffer with a maximum size of 64 8 bit. the size of the elastic buffer can be configured independently for the receive and transmit direction. programming of the receive buffer size is done by sic1.rbs1/0: rbs1/0 = 00: two frame buffer or 512 bits maximum of wander amplitude (peak-to-peak): 190 ui (1 ui = 488 ns) average delay after performing a slip: 1 frame or 256 bits rbs1/0 = 01: one frame buffer or 256 bits maximum of wander amplitude: 100 ui average delay after performing a slip: 128 bits, (sypr = output) rbs1/0 = 10: short buffer or 96 bits maximum of wander amplitude: 38 ui average delay after performing a slip: 48 bits, (sypr = output) rbs1/0 = 11: bypass of the receive elastic buffer the buffer functions are: clock adaption between system clock (sclkr) and internally generated route clock (rclk). compensation of input wander and jitter. frame alignment between system frame and receive route frame falc ? 56 pef 2256 h/e functional description e1 user?s manual 75 ds1.1, 2003-10-23 hardware description reporting and controlling of slips controlled by special signals generated by the receiver, the unipolar bit stream is converted into bit-parallel data which is circularly written to the elastic buffer using internally generated receive route clock (rclk). reading of stored data is controlled by the system clock sourced by sclkr or by the receive jitter attenuator and the synchronization pulse (sypr ) together with the programmed offset values for the receive time slot/clock slot counters. after conversion into a serial data stream, the data is given out on port rdo. if the receive buffer is bypassed, programming of the time slot offset is disabled and data is clocked off with rclk instead of sclkr. in one frame or short buffer mode the delay through the receive buffer is reduced to an average delay of 128 or 46 bits. in bypass mode the time slot assigner is disabled. in this case sypr programmed as input is ignored. slips are performed in all buffer modes except bypass mode. after a slip is detected the read pointer is adjusted to one half of the current buffer size. table 16 gives an overview of the receive buffer operating mode. i in single frame mode (sic1.rbs), values of receive time slot offset (rc1/0) have to be specified great enough to prevent too great approach of frame begin of line side and frame begin of system side. figure 22 gives an idea of operation of the receive elastic buffer: a slip condition is detected when the write pointer (w) and the read pointer (r) of the memory are nearly coincident, i.e. the read pointer is within the slip limits (s +, s ?). if a slip condition is detected, a negative slip (one frame or one half of the current buffer size table 16 receive buffer operating modes (e1) buffer size (sic1.rbs1/0) ts offset programming (rc1/0) + sypr = input slip performance bypass 1) 1) in bypass mode the clock provided on pin sclkr is ignored. clocking is done with rclk. disabled recommended: sypr = output no short buffer not recommended, recommended: sypr = output yes 1 frame not recommended, recommended: sypr = output yes 2 frames enabled yes falc ? 56 pef 2256 h/e functional description e1 user?s manual 76 ds1.1, 2003-10-23 hardware description is skipped) or a positive slip (one frame or one half of the current buffer size is read out twice) is performed at the system interface, depending on the difference between rclk and the current working clock of the receive backplane interface. i.e. on the position of pointer r and w within the memory. a positive/negative slip is indicated in the interrupt status bits isr3.rsp and isr3.rsn. figure 22 the receive elastic buffer as circularly organized memory limits for slip detection (mode dependent) read pointer (system clock controlled) write pointer (route clock controlled) r? s+, s- r : : w: frame 2 time slots s- r frame 1 time slots moment of slip detection itd10952 w s+ slip falc ? 56 pef 2256 h/e functional description e1 user?s manual 77 ds1.1, 2003-10-23 hardware description 4.1.15 receive signaling controller (e1) the signaling controller can be programmed to operate in various signaling modes. the falc ? 56 performs the following signaling and data link methods. 4.1.15.1 hdlc or lapd access the falc ? 56 offers three independent hdlc channels. any hdlc channel can be attached either to the line side ("normal hdlc") or to the system side ("inverse hdlc"). each of them provides the following features: 64 byte receive fifo for each channel 64 byte transmit fifo for each channel transmission in one of 31 time slots (time slot number programmable for each channel individually) transmission in even frames only, odd frames only or both (programmable for each channel individually) bit positions to be used in selected time slots are maskable (any bit position can be enabled for each channel individually) hdlc or transparent mode flag detection crc checking bit-stuffing flexible address recognition (1 byte, 2 bytes) c/r-bit processing (according to lapd protocol) in addition to this, hdlc channel 1 provides: ss7 support bom (bit oriented message) support use of time slot 0 (up to 32 time slots) use of s a -bits flexibility to insert and extract data during certain time slots, any combination of time slots can be programmed independently for the receive and transmit direction in case of common channel signaling the signaling procedure hdlc/sdlc or lapd according to q.921 is supported. the signaling controller of the falc ? 56 performs the flag detection, crc checking, address comparison and zero-bit removing. the received data flow and the address recognition features can be performed in very flexible way, to satisfy almost any practical requirements. depending on the selected address mode, the falc ? 56 performs a 1 or 2-byte address recognition. if a 2-byte address field is selected, the high address byte is compared with the fixed value feh or fch (group address) as well as with two individually programmable values in rah1 and rah2 registers. according to the isdn lapd protocol, bit 1 of the high byte address is interpreted as command/response bit (c/r) and is excluded from the address comparison. buffering of receive data is done in a 64 byte deep rfifo. in signaling controller transparent mode, fully transparent data reception without hdlc falc ? 56 pef 2256 h/e functional description e1 user?s manual 78 ds1.1, 2003-10-23 hardware description framing is performed, i.e. without flag recognition, crc checking or bit stuffing. this allows user specific protocol variations. 4.1.15.2 support of signaling system #7 the hdlc controller of channel 1 supports the signaling system #7 (ss7) which is described in itu-q.703. the following description assumes, that the reader is familiar with the ss7 protocol definition. ss7 support must be activated by setting the mode register. the ss7 protocol is supported by the following hardware features in receive mode: all signaling units (su) are stored in the receive fifo (rfifo) detecting of flags from the incoming data stream bit stuffing (zero deletion) checking of seven or more consecutive ones in the receive data stream checking if the received signaling unit is a multiple of eight bits and at least six octets including the opening flag calculation of the crc16 checksum: in receive direction the calculated checksum is compared to the received one; errors are reported in register rsis. checking if the signal information field of a received signaling unit consists of more than 272 octets, in this case the current signaling unit is discarded. in order to reduce the microprocessor load, fill in signaling units (fisus) are processed automatically. by examining the length indicator of a received signal unit the falc ? 56 decides whether a fisu has been received. consecutively received fisus are compared and optionally not stored in the receive fifo (rfifo, 2 32 bytes), if the contents is equal to the previous one. the same applies to link status signaling units, if bit ccr5.csf is set. the different types of signaling units as message signaling unit (msu), link status signaling unit (lssu) and fill in signaling units (fisu) are indicated in the rsis register, which is automatically added to the rfifo with each received signaling unit. the complete signaling unit except start and end flags is stored in the receive fifo. the functions of bits ccr1.rcrc and ccr1.radd are still valid in ss7 mode. errored signaling units are handled automatically according to itu-t q.703 as shown in figure 23 . su counter (su) and errored su counter (c s ) are reset by setting cmdr2.rsuc. the error threshold t can be selected to be 64 (default) or 32 by setting/clearing bit ccr5.suet. if the defined error limit is exceeded, an interrupt (isr1.suex) is generated, if not masked by imr1.suex = 1. note: if suex is caused by an aborted/invalid frame, the interrupt will be issued regularly until a valid frame is received (e.g. a fisu). falc ? 56 pef 2256 h/e functional description e1 user?s manual 79 ds1.1, 2003-10-23 hardware description figure 23 automatic handling of errored signaling units reset counter values c s := 0 su := 0 [cmdr2.rsuc = 1] idle in service su in error? c s := c s + 1 su := su + 1 su := su + 1 c s = t ? su = 256 ? su := 0 c s = 0 ? c s := c s -1 in service link failure [isr1.suex = 1] idle notes : su: signaling units counter c s : errored signaling units counter t: error threshold (64 or 32), selectable by ccr5.suet n n n n y y y y f0071 falc ? 56 pef 2256 h/e functional description e1 user?s manual 80 ds1.1, 2003-10-23 hardware description 4.1.15.3 s a -bit access (e1) the falc ? 56 supports the s a -bit signaling of time slot 0 of every other frame as follows: the access through register rsw the access through registers rsa(8:4), capable of storing the information for a complete multiframe the access through the 64 byte deep receive fifo of the signaling controller of hdlc channel 1. this s a -bit access gives the opportunity to receive a transparent bit stream as well as hdlc frames where the signaling controller automatically processes the hdlc protocol. any combination of s a -bits which shall be extracted and stored in the rfifo is selected by xc0.sa(8:4). the access to the rfifo is supported by isr0.rme/rpf. 4.1.15.4 channel associated signaling cas (e1, serial mode) the signaling information is carried in time slot 16 (ts16). the signaling controller samples the bit stream either on the receive line side or if external signaling is enabled on the receive system side. external signaling is enabled by selecting the rsig pin function in registers pc(4:1) and setting xsp.casen = 1. optionally the complete cas multiframe can be transmitted on pin rsig. the signaling data is clocked with the working clock of the receive highway (sclkr) together with the receive synchronization pulse (sypr ). data on rsig is transmitted in the last 4 bits per time slot and is aligned to the data on rdo. the first 4 bits per time slot can be optionally fixed high or low (sic2.ssf), except for time slot 0 and 16 (bit 1 to 4 are always "0000" in ts16). in time slot 0 the fas/nfas word is transmitted, in time slot 16 the cas multiframe pattern "0000xyxx". data on rsig is only valid if the freeze signaling status is inactive. with fmr1.sais an all-ones data stream can be transmitted on rdo and rsig. the signaling procedure is done as it is described in itu-t g.704 and g.732. the main functions are: synchronization to a cas multiframe detection of ais and remote alarm in cas multiframes separation of cas service bits x1 to x3 updating of the received signaling information is controlled by the freeze signaling status. the freeze signaling status is automatically activated if a loss-of-signal (frs0.los = 1), or a loss of cas multiframe alignment (frs1.tsl16lfa = 1) or a receive slip occurs. the current freeze status is output on port freeze (rp(a:d)) and indicated by register sis.sfs. optionally automatic freeze signaling can be disabled by setting bit sic3.daf. after cas resynchronization an interrupt is generated. because at this time the signaling is still frozen, cas data is not valid yet. read out of cas data has to be delayed until the next cas multiframe is received. falc ? 56 pef 2256 h/e functional description e1 user?s manual 81 ds1.1, 2003-10-23 hardware description because the cas controller is working on the pcm highway side of the receive buffer, slips disturb the cas data. figure 24 2.048 mhz receive signaling highway (e1) 4.1.15.5 channel associated signaling cas (e1, p access mode) the signaling information is carried in time slot 16 (ts16). receive data is stored in registers rs(16:1) aligned to the cas multiframe boundary. the signaling controller samples the bit stream either on the receive line side or if external signaling is enabled on the receive system side. the signaling procedure is done as it is described in itu-t g.704 and g.732. the main functions are: synchronization to a cas multiframe detection of ais and remote alarm in cas multiframes separation of cas service bits x1 to x3 storing of received signaling data in registers rs(16:1) with last look capability updating of the received signaling information is controlled by the freeze signaling status. the freeze signaling status is automatically activated if a loss-of-signal (frs0.los = 1), or a loss of cas multiframe alignment (frs1.tsl16lfa = 1) or a receive slip occurs. the current freeze status is output on port freeze (rp(a:d)) and indicated by register sis.sfs. optionally automatic freeze signaling can be disabled by setting bit sic3.daf. if sis.sfs is active, updating of the registers rs(16:1) is disabled. to relieve the p load from always reading the complete rs(16:1) buffer every 2 ms the falc ? 56 notifies the p through interrupt isr0.casc only when signaling changes f0133 a b c d a b c d 4 5 6 7 0 1 2 3 4 5 6 7 ts31 ts0 ts1 0 0 0 0 x y x x 0 1 2 3 4 5 6 7 ts16 a b c d 0 1 2 3 4 5 6 7 ts31 rsig rdo sclkr fas/nfas fas/nfas sypr t 125 s t = time slot offset (rc0, rc1) fas = frame alignment signal nfas = ts0 not containing fas abcd = signaling bits for time slots 1...15 and 17...31 of cas multiframe 0000xyxx = cas multiframe alignment signal in ts16 falc ? 56 pef 2256 h/e functional description e1 user?s manual 82 ds1.1, 2003-10-23 hardware description from one multiframe to the next. additionally the falc ? 56 generates a receive signaling data change pointer (rsp1/2) which directly points to the updated rs(16:1) register. because the cas controller is working on the pcm highway side of the receive buffer, slips disturb the cas data. 4.2 framer operating modes (e1) 4.2.1 general bit: fmr1.pmod = 0 pcm line bit rate : 2.048 mbit/s single frame length : 256 bit, no. 1?256 framing frequency : 8 khz hdlc controller : n 64 kbit/s, n = 1 to 32 or n 4 kbit/s, n = 1 to 5 organization : 32 time slots, no. 0?31 with 8 bits each, no. 1?8 the operating mode of the falc ? 56 is selected by programming the carrier data rate and characteristics, line code, multiframe structure, and signaling scheme. the falc ? 56 implements all of the standard framing structures for e1 or pcm 30 (cept, 2.048 mbit/s) carriers. the internal hdlc or cas controller supports all signaling procedures including signaling frame synchronization/synthesis and signaling alarm detection in all framing formats. the time slot assignment from the pcm line to the system highway and vice versa is performed without any changes of numbering (ts0 ? ts0, ?, ts31 ? ts31). summary of e1 framing modes doubleframe format according to itu-t g. 704 multiframe format according to itu-t g. 704 crc4 processing according to itu-t g. 706 multiframe format with crc4 to non crc4 interworking according to itu-t g. 706 multiframe format with modified crc4 to non crc4 interworking multiframe format with crc4 performance monitoring after reset, the falc ? 56 is switched into doubleframe format automatically. switching between the framing formats is done by programming bits fmr2.rfs1/0 and fmr3.extiw for the receiver and fmr1.xfs for the transmitter. falc ? 56 pef 2256 h/e functional description e1 user?s manual 83 ds1.1, 2003-10-23 hardware description 4.2.2 doubleframe format (e1) the framing structure is defined by the contents of time slot 0 (refer to table 17 ). table 17 allocation of bits 1 to 8 of time slot 0 (e1) bit alternatenumber frames 12 345678 frame containing the frame alignment signal s i 0 011011 note 1) frame alignment signal frame not containing the frame alignment signal or service word s i 1as a4 s a5 s a6 s a7 s a8 note 1) 1) s i -bits: reserved for international use. if not used, these bits should be fixed to "1". access to received information trough bits rsw.rsi and rsp.rsif. transmission is enabled by bits xsw.xsis and xsp.xsif. note 2) 2) fixed to "1". used for synchronization. note 3) 3) remote alarm indication: in undisturbed operation "0"; in alarm condition "1". note 4) 4) s a -bits: reserved for national use. if not used, they should be fixed at "1". access to received information trough bits rsw.ry0?4. transmission is enabled by bits xsw.xy0?4. hdlc signaling in bits s a 4 to 8 is selectable. as a special extension for double frame format, the s a -bit registers rsa4 to 8/xsa4 to 8 can be used optionally. falc ? 56 pef 2256 h/e functional description e1 user?s manual 84 ds1.1, 2003-10-23 hardware description 4.2.2.1 transmit transparent modes in transmit direction, contents of time slot 0 frame alignment signal of the outgoing pcm frame are normally generated by the falc ? 56. however, transparency for the complete time slot 0 can be achieved by selecting the transparent mode xsp.tt0. with the transparent service word mask register tswm the s i -bits, a-bit and the s a -bits can be selectively switched through transparently. 4.2.2.2 synchronization procedure synchronization status is reported by bit frs0.lfa. framing errors are counted by the framing error counter (fec). asynchronous state is reached after detecting 3 or 4 consecutive incorrect fas words or 3 or 4 consecutive incorrect service words (bit 2 = 0 in time slot 0 of every other frame not containing the frame alignment word), the selection is done by bit rc0.asy4. additionally, the service word condition can be disabled. when the framer lost its synchronization an interrupt status bit isr2.lfa is generated. in asynchronous state, counting of framing errors and detection of remote alarm is stopped. ais is automatically sent to the backplane interface (can be disabled by bit fmr2.dais). further on the updating of the registers rsw, rsp, rsa(8:4), rsa6s and rs(16:1) is halted (remote alarm indication, s a /s i -bit access). the resynchronization procedure starts automatically after reaching the asynchronous state. additionally, it can be invoked user controlled by bit fmr0.frs (force resynchronization, the fas word detection is interrupted until the framer is in the asynchronous state. after that, resynchronization starts automatically). synchronous state is established after detecting: a correct fas word in frame n, table 18 transmit transparent mode (doubleframe e1) enabled by transmit transparent source for framing a-bit s a -bits s i -bits ? xsp.tt0 tswm.tsif tswm.tsis tswm.tra tswm.tsa(8:4) (int. gen.) via pin xdi 1) (int. gen.) (int. gen.) (int. gen.) (int. gen.) 1) pin xdi or xsig or xfifo buffer (signaling controller) xsw.xra 2) via pin xdi xsw.xra xsw.xra via pin xdi xsw.xra 2) additionally, automatic transmission of the a-bit is selectable. xsw.xy0?4 3) via pin xdi xsw.xy0?4 xsw.xy0?4 xsw.xy0?4 via pin xdi 3) as a special extension for double frame format, the s a -bit register can be used optionally. xsw.xsis, xsp.xsif via pin xdi via pin xdi via pin xdi xsw.xsis, xsp.xsif xsw.xsis, xsp.xsif falc ? 56 pef 2256 h/e functional description e1 user?s manual 85 ds1.1, 2003-10-23 hardware description the presence of the correct service word (bit 2 = 1) in frame n + 1, a correct fas word in frame n + 2. if the service word in frame n + 1 or the fas word in frame n + 2 or both are not found searching for the next fas word starts in frame n + 2 just after the previous frame alignment signal. reaching the synchronous state causes a frame alignment recovery interrupt status isr2.far if enabled. undisturbed operation starts with the beginning of the next doubleframe. 4.2.2.3 a-bit access if the falc ? 56 detects a remote alarm indication in the received data stream the interrupt status bit isr2.ra is set. with setting of bit xsw.xra a remote alarm (rai) is sent to the far end. by setting fmr2.axra the falc ? 56 automatically transmit the remote alarm bit = 1 in the outgoing data stream if the receiver detects a loss of frame alignment frs0.lfa = 1. if the receiver is in synchronous state frs0.lfa = 0 the remote alarm bit is reset. note: the a-bit can be processed by the system interface. setting bit tswm.tra enables transparency for the a-bit in transmit direction (refer to table 17 ). 4.2.2.4 s a -bit access as an extension for access to the s a -bits through registers rsa(8:4)/xsa(8:4) an option is implemented to allow the usage of internal s a -bit registers rsa(8:4)/xsa(8:4) in doubleframe format. this function is enabled by setting fmr1.ensa = 1 for the transmitter and fmr1.rfs(1:0) = 01 for the receiver. in this case the falc ? 56 internally works with a 16-frame structure but no crc multiframe alignment/generation is performed. falc ? 56 pef 2256 h/e functional description e1 user?s manual 86 ds1.1, 2003-10-23 hardware description 4.2.3 crc-multiframe (e1) the multiframe structure shown in table 19 is enabled by setting bit: fmr2.rfs1/0 for the receiver and fmr1.xfs for the transmitter. multiframe : 2 submultiframes = 2 8 frames frame alignment : refer to section doubleframe format multiframe alignment : bit 1 of frames 1, 3, 5, 7, 9, 11 with the pattern "001011" crc bits : bit 1 of frames 0, 2, 4, 6, 8, 10, 12, 14 crc block size : 2048 bit (length of a submultiframe) crc procedure : crc4, according to itu-t g.704 and g.706 e: spare bits for international use. access to received information through bits rsp.rs13 and rsp.rs15. transmission is enabled by bits xsp.xs13 and xsp.xs15. additionally, automatic transmission for submultiframe error indication is selectable. s a : spare bits for national use. additionally, s a -bit access through registers rsa4?8 and xsa4?8 is provided. hdlc-signaling in bits s a 4 to s a 8 is selectable. c 1 ?c 4 : cyclic redundancy check bits. a: remote alarm indication. additionally, automatic transmission of the a-bit is selectable. table 19 crc-multiframe structure (e1) sub- multiframe frame number bits 1 to 8 of the frame 123456 78 multiframe i 0 1 2 3 4 5 6 7 c 1 0 c 2 0 c 3 1 c 4 0 0 1 0 1 0 1 0 1 0 a 0 a 0 a 0 a 1 s a4 1 s a4 1 s a4 1 s a4 1 s a5 1 s a5 1 s a5 1 s a5 0 s a61 0 s a62 0 s a63 0 s a64 1 s a7 1 s a7 1 s a7 1 s a7 1 s a8 1 s a8 1 s a8 1 s a8 ii 8 9 10 11 12 13 14 15 c 1 1 c 2 1 c 3 e* c 4 e* 0 1 0 1 0 1 0 1 0 a 0 a 0 a 0 a 1 s a4 1 s a4 1 s a4 1 s a4 1 s a5 1 s a5 1 s a5 1 s a5 0 s a61 0 s a62 0 s a63 0 s a64 1 s a7 1 s a7 1 s a7 1 s a7 1 s a8 1 s a8 1 s a8 1 s a8 falc ? 56 pef 2256 h/e functional description e1 user?s manual 87 ds1.1, 2003-10-23 hardware description for transmit direction, contents of time slot 0 are additionally determined by the selected transparent mode. the crc procedure is automatically invoked when the multiframe structure is enabled. crc errors in the received data stream are counted by the 16-bit crc error counter cec (one error per submultiframe, maximum). additionally a crc4 error interrupt status isr0.crc4 is generated if enabled by imr0.crc4. all crc bits of one outgoing submultiframe are automatically inverted in case a crc error is flagged for the previous received submultiframe. this function is enabled by bit rc0.crci. setting of bit rc0.xcrci inverts the crc bits before transmission to the distant end. the function of rc0.xcrci and rc0.crci are logically ored. 4.2.3.1 synchronization procedure multiframe alignment is assumed to have been lost if doubleframe alignment has been lost (flagged on status bit frs0.lfa). the rising edge of this bit causes an interrupt. the multiframe resynchronization procedure starts when doubleframe alignment has been regained which is indicated by an interrupt status bit isr2.far. for doubleframe synchronization refer to section doubleframe format. it is also be invoked by the user by setting bit fmr0.frs for complete doubleframe and multiframe resynchronization bit fmr1.mfcs for multiframe resynchronization only. the crc checking mechanism is enabled after the first correct multiframe pattern has been found. however, crc errors are not counted in asynchronous state. table 20 transmit transparent mode (crc multiframe e1) enabled by transmit transparent source for framing + crc a-bit s a -bits e-bits ? xsp.tt0 tswm.tsif tswm.tsis tswm.tra tswm.tsa(8:4) (int. gen.) via pin xdi 1) via pin xdi via pin xdi (int. gen.) (int. gen.) 1) pin xdi or xsig or xfifo buffer (signaling controller) xsw.xra 2) via pin xdi xsw.xra 1) xsw.xra 1) via pin xdi xsw.xra 1) 2) automatic transmission of the a-bit is selectable xsw.xy0 ? 4 3) via pin xdi xsw.xy0 ? 4 2) xsw.xy0 ? 4 2) xsw.xy0 ? 4 2) via pin xdi 3) the s a -bit register xsa(8:4) can be used optionally xsp.xs13/xs15 4) via pin xdi (int. generated) via pin xdi xsp.xs13/xs15 3) xsp.xs13/xs15 3) 4) additionally, automatic transmission of submultiframe error indication is selectable falc ? 56 pef 2256 h/e functional description e1 user?s manual 88 ds1.1, 2003-10-23 hardware description in doubleframe asynchronous state, counting of framing errors, crc4 bit errors and detection of remote alarm is stopped. ais is automatically sent to the backplane interface (can be disabled by bit fmr2.dais). further on the updating of the registers rsw, rsp, rsa(8:4), rsa6s and rs(16:1) is halted (remote alarm indication, s a /s i -bit access). the multiframe synchronous state is established after detecting two correct multiframe alignment signals at an interval of n 2 ms (n = 1, 2, 3 ?). the loss of multiframe alignment flag frs0.lmfa is reset. additionally an interrupt status multiframe alignment recovery bit isr2.mfar is generated with the falling edge of bit frs0.lmfa. 4.2.3.2 automatic force resynchronization (e1) in addition, a search for doubleframe alignment is automatically initiated if two multiframe pattern with a distance of n 2 ms have not been found within a time interval of 8 ms after doubleframe alignment has been regained (bit fmr1.afr). a new search for frame alignment is started just after the previous frame alignment signal. 4.2.3.3 floating multiframe alignment window (e1) after reaching doubleframe synchronization a 8 ms timer is started. if a multiframe alignment signal is found during the 8 ms time interval the internal timer is reset to remaining 6 ms in order to find the next multiframe signal within this time. if the multiframe signal is not found for a second time, the interrupt status bit isr0.t8ms is set. this interrupt usually occurs every 8 ms until multiframe synchronization is achieved. 4.2.3.4 crc4 performa nce monitoring (e1) in the synchronous state checking of multiframe pattern is disabled. however, with bit fmr2.almf an automatic multiframe resynchronization mode can be activated. if 915 out of 1000 errored crc submultiframes are found then a false frame alignment is assumed and a search for doubleframe and multiframe pattern is initiated. the new search for frame alignment is started just after the previous basic frame alignment signal. the internal crc4 resynchronization counter is reset when the multiframe synchronization has been regained. 4.2.3.5 modified crc4 multifra me alignment algorithm (e1) the modified crc4 multiframe alignment algorithm allows an automatic interworking between framers with and without a crc4 capability. the interworking is realized as it is described in itu-t g.706 appendix b. if doubleframe synchronization is consistently present but crc4 multiframe alignment is not achieved within 400 ms it is assumed that the distant end is initialized to doubleframe format. the crc4/non-crc4 interworking is enabled by fmr2.rfs1/0 = 11 and is activated only if the receiver has lost its synchronization. if doubleframe alignment (basic falc ? 56 pef 2256 h/e functional description e1 user?s manual 89 ds1.1, 2003-10-23 hardware description frame alignment) is established, a 400-ms timer and searching for multiframe alignment are started. a research for basic frame alignment is initiated if the crc4 multiframe synchronization cannot be achieved within 8 ms and is started just after the previous frame alignment signal. the research of the basic frame alignment is done in parallel and is independent of the synchronization procedure of the primary basic frame alignment signal. during the parallel search all receiver functions are based on the primary frame alignment signal, like framing errors, s a -, s i -, a-bits, ?). all subsequent multiframe searches are associated with each basic framing sequence found during the parallel search. if the crc4 multiframe alignment sequence was not found within the time interval of 400 ms, the receiver is switched into a non-crc4 mode indicated by setting the bit frs0.nmf (no multiframing found) and isr2.t400ms. in this mode checking of crc bits is disabled and the received e-bits are forced to low. the transmitter framing format is not changed. even if multiple basic fas resynchronizations have been established during the parallel search, the receiver is maintained to the initially determined primary frame alignment signal location. however, if the crc4-multiframe alignment can be achieved within the 400 ms time interval assuming a crc4-to-crc4 interworking, then the basic frame alignment sequence associated to the crc4 multiframe alignment signal is chosen. if necessary, the primary frame alignment signal location is adjusted according to the multiframe alignment signal. the crc4 performance monitoring is started if enabled by fmr2.almf and the received e-bits are processed in accordance to itu-t g.704. switching into the doubleframe format (non-crc4) mode after 400 ms can be disabled by setting of fmr3.extiw. in this mode the falc ? 56 continues to search for multiframing. in the interworking mode setting of bit fmr1.afr is not allowed. 4.2.3.6 a-bit access (e1) if the falc ? 56 detects a remote alarm indication (bit 2 in ts0 not containing the fas word) in the received data stream the interrupt status bit isr2.ra is set. with the deactivation of the remote alarm the interrupt status bit isr2.rar is generated. by setting fmr2.axra the falc ? 56 automatically transmits the remote alarm bit = 1 in the outgoing data stream if the receiver detects a loss of frame alignment (frs0.lfa = 1). if the receiver is in synchronous state (frs0.lfa = 0), the remote alarm bit is reset in the outgoing data stream. additionally, if bit fmr3.extiw is set and the multiframe synchronous state cannot be achieved within 400 ms after finding the primary basic framing, the a-bit is transmitted active high to the remote end until the multiframing is found. note: the a-bit can be processed by the system interface. setting bit tswm.tra enables transparency for the a-bit in transmit direction (refer to table 19 ). falc ? 56 pef 2256 h/e functional description e1 user?s manual 90 ds1.1, 2003-10-23 hardware description 4.2.3.7 s a -bit access (e1) due to signaling procedures using the five s a -bits (s a4 ?s a8 ) of every other frame of the crc multiframe structure, three possibilities of access by the microprocessor are implemented. the standard procedure allows reading/writing the s a -bit registers rsw, xsw without further support. the s a -bit information is updated every other frame. the advanced procedure, enabled by bit fmr1.ensa, allows reading/writing the s a -bit registers rsa4?8, xsa4?8. a transmit or receive multiframe begin interrupt (isr0.rmb or isr1.xmb) is provided. registers rsa(8:4) contains the service word information of the previously received crc-multiframe or 8 doubleframes (bit slots 4 to 8 of every service word). these registers are updated with every mult iframe begin interrupt isr0.rmb. with the transmit multiframe begin an interrupt isr1.xmb is generated and the contents of the registers xsa(8:4) is copied into sha dow registers. the contents is subsequently sent out in the service words of the next outgoing crc multiframe (or every doubleframe) if none of the time slot 0 transparent modes is enabled. the transmit multiframe begin interrupt xmb request that these registers issue should be serviced. if requests for new information are ignored, the current contents is repeated. the extended access through the receive and transmit fifos of the signaling controller. in this mode it is possible to transmit/receive a hdlc frame or a transparent bit stream in any combination of the s a -bits. enabling is done by setting of bit ccr1.eits and the corresponding bits xc0.sa8e to sa4e/tswm.tsa8 to tsa4 and resetting of registers ttr(4:1), rtr(4:1) and fmr1.ensa. the access to and from the fifos is supported by isr0.rme, rpf and isr1.xpr, als. s a 6-bit detection according to ets 300233 four consecutive received s a 6-bits are checked for the combinations defined by ets 300233. the falc ? 56 detects the following fixed s a 6-bit combinations: sa61, sa62, sa63, sa64 = 1000, 1010, 1100, 1110, 1111. all other possible 4-bit combinations are grouped to status ?x?. a valid s a 6-bit combination must occur three times in a row. the corresponding status bit in register rsa6s is set. register rsa6s is of type ?clear on read?. any status change of the s a 6-bit combinations causes an interrupt (isr0.sa6sc). during the basic frame asynchronous state update of register rsa6s and interrupt status isr0.sa6sc is disabled. in multiframe format the detection of the s a 6-bit combinations can be done either synchronously or asynchronously to the submultiframe (fmr3.sa6sy). in synchronous detection mode updating of register rsa6s is done in the multiframe synchronous state (frs0.lmfa = 0). in asynchronous detection mode updating is independent of the multiframe synchronous state. falc ? 56 pef 2256 h/e functional description e1 user?s manual 91 ds1.1, 2003-10-23 hardware description s a 6-bit error indication counters the s a 6-bit error indication counter crc2l/h (16 bits) counts the received s a 6-bit sequence 0001 or 0011 in every crc submulti frame. in the primary rate access digital section this counter option gives informat ion about crc errors reported from the te by the s a 6 bit. incrementing is only possible in the multiframe synchronous state. the s a 6-bit error indication counter crc3l/h (16 bits) counts the received s a 6-bit sequence 0010 or 0011 in every crc submultiframe. in the primary rate access digital section this counter option gives information about crc errors detected at t-reference point and reporting them by the s a 6-bit. incrementing is only possible in the multiframe synchronous state. 4.2.3.8 e-bit access (e1) due to signaling requirements, the e-bits of frame 13 and frame 15 of the crc multiframe can be used to indicate received errored submultiframes: submultiframe i statuse-bit located in frame 13 submultiframe ii statuse-bit located in frame 15 no crc error: e = 1; crc error:e = 0 standard procedure after reading the submultiframe error indication rsp.si1 and rsp.si2, the microprocessor has to update the contents of register xsp (xs13, xs15). access to these registers has to be synchronized on transmit or receive multiframe begin interrupts (isr0.rmb or isr1.xmb). automatic mode in the multiframe synchronous state the e-bits are processed according to itu-t g.704 independently of bit xsp.ebp (e-bit polarity selection). by setting bit xsp.axs status information of received submultiframes is automatically inserted in the e-bit position of the outgoing crc multiframe without any further interventions of the microprocessor. in the doubleframe and multiframe asynchronous state the e-bits are set or cleared, depending on the setting of bit xsp.ebp. submultiframe error indication counter the ebc (e-bit) counter ebcl/h (16 bits) counts zeros in the e-bit position of frame 13 and 15 of every received crc multiframe. this counter option gives information about the outgoing transmit pcm line if the e-bits are used by the remote end for submultiframe error indication. incrementing is only possible in the multiframe synchronous state. falc ? 56 pef 2256 h/e functional description e1 user?s manual 92 ds1.1, 2003-10-23 hardware description note: e-bits can be processed by the system interface. setting bit tswm.tsis enables transparency for e-bits in transmit direction (refer to table 19 ). figure 25 crc4 multiframe alignment recovery algorithms (e1) itd10310 out of primary bfa: inhibit incoming crc-4 performance monitoring reset all timers set frs0.lfa/lmfa/nmf = 110 no bfa search ? primary yes reset internal frame alignment status start 400 ms timer in primary bfa: enable primary bfa loss checking process (frs0.lfa = 0) start 8 ms timer can crc-4 mfa be found yes in 8 ms ? 400 ms timer elapsed ? yes no parallel bfa search good ? no no assume crc-4 to crc-4 interworking: confirm primary bfa associated with crc-4 mfa reset internal multiframe alignment status adjust primary bfa if necessary (frs0.lmfa = 0) confirm primary bfa set internal 400 ms timer expiration status bit assume crc-4 to non crc-4 interworking: (frs0.nmf = 1) start crc-4 performance monitoring yes or lfa ? error count crc-4 no continue crc-4 performance monitoring _ < 915 yes crc-4 mfa search falc ? 56 pef 2256 h/e functional description e1 user?s manual 93 ds1.1, 2003-10-23 hardware description 4.3 additional receive framer functions (e1) 4.3.1 error performance monitoring and alarm handling alarm indication signal: detection and recovery is flagged by bit frs0.ais and isr2.ais. transmission is enabled by bit fmr1.xais. loss-of-signal: detection and recovery is flagged by bit frs0.los and isr2.los. remote alarm indication: detection and release is flagged by bit frs0.rra, rsw.rra and isr2.ra/rar. transmission is enabled by bit xsw.xra. ais in time slot 16: detection and release is flagged by bit frs1.ts16ais and isr3.ais16. transmission is enabled by writing all ones in registers xs(16:1). los in time slot 16: detection and release is flagged by bit frs1.ts16los. transmission is enabled by writing all zeros in registers xs(16:1). remote alarm in time slot 16: detection and release is flagged by bit frs1.ts16ra and isr3.ra16. transmission is enabled by bit xs1.2. transmit line shorted: detection and release is flagged by bit frs1.xls and isr1.xlsc. transmit ones-density: detection and release is flagged by bit frs1.xlo and isr1.xlsc. table 21 summary of alarm detection and release (e1) alarm detection condition clear condition loss-of-signal (los) no transitions (logical zeros) in a programmable time interval of 16 to 4096 consecutive pulse periods. programmable receive input signal threshold programmable number of ones (1 to 256) in a programmable time interval of 16 to 4096 consecutive pulse periods. a one is a signal with a level above the programmed threshold. alarm indication signal (ais) fmr0.alm = 0: less than 3 zeros in 250 s and loss of frame alignment declared fmr0.alm = 1: less than 3 zeros in each of two consecutive 250-s periods fmr0.alm = 0: more than 2 zeros in 250 s fmr0.alm = 1: more than 2 zeros in each of two 500-s periods remote alarm (rra) bit 3 = 1 in time slot 0 not containing the fas word set conditions no longer detected. falc ? 56 pef 2256 h/e functional description e1 user?s manual 94 ds1.1, 2003-10-23 hardware description 4.3.2 auto modes 4.3.2.1 automatic remote alarm access if the receiver has lost its synchronization a remote alarm can be sent automatically, if enabled by bit fmr2.axra to the distant end. the remote alarm bit is set automatically in the outgoing data stream, if the receiver is in asynchronous state (frs0.lfa bit is set). in synchronous state the remote alarm bit is removed. 4.3.2.2 automatic e-bit access by setting bit xsp.axs status information of received submultiframes is automatically inserted at the e-bit position of the outgoing crc multiframe without any further interventions of the microprocessor. 4.3.2.3 automatic ais to system interface in asynchronous state the synchronizer enforces an ais to the receive system interface automatically. however, received data can be switched through transparently, if bit fmr2.dais is set. remote alarm in time slot 16 (ts16ra) y-bit = 1 received in cas multiframe alignment word y-bit = 0 received in cas multiframe alignment word loss-of-signal in time slot 16 (ts16los) all zeros for at least 16 consecutively received time slots 16 receiving a one in time slot 16 alarm indication signal in time slot 16 (ts16ais) time slot 16 containing less than 4 zeros in each of two consecutive cas multiframes periods time slot 16 containing more than 3 zeros in one cas multiframe transmit line short (xls) more than 3 pulse periods with highly increased transmit line current on xl1/2 transmit line current limiter inactive transmit ones-density (xlo) 32 consecutive zeros in the transmit data stream on xl1/2 cleared with each transmitted pulse table 21 summary of alarm detection and release (e1) (cont?d) alarm detection condition clear condition falc ? 56 pef 2256 h/e functional description e1 user?s manual 95 ds1.1, 2003-10-23 hardware description 4.3.2.4 automatic clock source switching in slave mode (lim0.mas = 0) the dco-r synchronizes to the recovered route clock. in case of loss-of-signal (los) the dco-r switches to master mode automatically. if bit cmr1.dcs is set, automatic switching from rclk to sync is disabled. 4.3.2.5 automatic freeze signaling updating of the received signaling information is controlled by the freeze signaling status. the freeze signaling status is automatically activated if a loss-of-signal or a loss of cas multiframe alignment or a receive slip occurs. the internal signaling buffer rs(16:1) is frozen. optionally automatic freeze signaling is disabled by setting bit sic3.daf. 4.3.3 error counters the falc ? 56 offers six error counters where each of them has a length of 16 bit. they record code violations, framing bit errors, crc4-bit errors and crc4 error events which are flagged in the different s a 6-bit combinations or the number of received multiframes in asynchronous state or the change of frame alignment (cofa). counting of the multiframes in the asynchronous state and the cofa parameter is done in a 6/2 bit counter and is shared with cec3l/h. each of the error counters is buffered. buffer updating is done in two modes: one-second accumulation on demand by handshake with writing to the dec register in the one-second mode an internal/external one-second timer updates these buffers and resets the counter to accumulate the error events in the next one-second period. the error counter cannot overflow. error even ts occurring during an error counter reset are not lost. 4.3.4 errored second the falc ? 56 supports the error performance monitoring by detecting the following alarms or error events in the received data: framing errors, crc errors, code violations, loss of frame alignment, loss-of-signal, alarm indication signal, e-bit error, receive and transmit slips. with a programmable interrupt mask register esm all these alarms or error events can generate an errored second interrupt (isr3.es) if enabled. 4.3.5 one-second timer additionally, a one-second timer interrupt can be generated internally to indicate that the enabled alarm status bits or the error counters have to be checked. the one-second timer signal is output on port sec/fsc (gpc1.csfp1/0). optionally synchronization to falc ? 56 pef 2256 h/e functional description e1 user?s manual 96 ds1.1, 2003-10-23 hardware description an external second timer is possible which has to be provided on pin sec/fsc. selecting the external second timer is done with gcr.ses. refer also to register gpc1 for input/output selection. 4.3.6 in-band loop generation and detection the falc ? 56 generates and detects a framed or unframed in-band loop-up (activate) and loop-down (deactivate) pattern with bit error rates up to 10 -2 . framed or unframed in-band loop code is selected by lcr1.fllb. replacing transmit data with the in-band loop codes is done by programming fmr3.xld/xlu. the falc ? 56 also offers the ability to generate and detect a flexible in-band loop-up and loop-down pattern (lcr1.llbp = 1). the loop-up and loop-down pattern is individually programmable from 2 to 8 bits in length (lcr1.lac1/0 and lcr1.ldc1/0). programming of loop codes is done in registers lcr2 and lcr3. status and interrupt status bits inform the user whether loop-up or loop-down code has been detected. 4.3.7 time slot 0 transparent mode the transparent modes are useful for loop-backs or for routing data unchanged through the falc ? 56. in receive direction, transparency for ternary or dual-/single-rail unipolar data is always achieved if the receiver is in the synchronous state. in asynchronous state data is transparently switched through if bit fmr2.dais is set. however, correct time slot assignment cannot be guaranteed due to missing frame alignment between line and system side. setting of bit loop.rtm disconnects control of the internal elastic store from the receiver. the elastic buffer is now in a ?free running? mode without any possibility to update the time slot assignment to a new frame position in case of resynchronization of the receiver. together with fmr2.dais this function can be used to realize undisturbed transparent reception. transparency in transmit direction can be achieved by activating the time slot 0 transparent mode (bit xsp.tt0 or tswm.(7:0)). if xsp.tt0 = 1 all internal information of the falc ? 56 (framing, crc, s a /s i -bit signaling, remote alarm) is ignored. with register tswm the s i -bits, a-bit or the s a -bits can be enabled selectively to send data transparently from port xdi to the far end. for complete transparency the internal signaling controller, idle code generation and ais alarm generation, single channel and payload loop-back have to be disabled. falc ? 56 pef 2256 h/e functional description e1 user?s manual 97 ds1.1, 2003-10-23 hardware description 4.4 transmit path in e1 mode 4.4.1 transmitter (e1) the serial bit stream is processed by the transmitter which has the following functions: frame/multiframe synthesis of one of the two selectable framing formats insertion of service and data link information ais generation (alarm indication signal) remote alarm generation crc generation and insertion of crc bits crc bits inversion in case of a previously received crc error idle code generation per ds0 the frame/multiframe boundaries of the tr ansmitter can be externally synchronized by using the sypx /xmfs pin. any change of the transmit time slot assignment subsequently produces a change in the framing bit positions on the line side. this feature is required if signaling and service bits are routed through the switching network and are inserted in transmit direction by the system interface. in loop-timed configuration (lim2.elt = 1) disconnecting the control of the transmit system highway from the transmitter is done by setting xsw.xtm. the transmitter is now in a free running mode without any possibility to update the multiframe position in case of changing the transmit time slot assignment. the framing bits are generated independently of the transmit system interface. for proper operation the transmit elastic buffer size should be programmed to 2 frames. the contents of selectable time slots can be overwritten by the pattern defined by register idle. the selection of ?idle chan nels? is done by programming the four-byte registers icb1?icb4. falc ? 56 pef 2256 h/e functional description e1 user?s manual 98 ds1.1, 2003-10-23 hardware description 4.4.2 transmit line interface (e1) the analog transmitter transforms the unipolar bit stream to ternary (alternate bipolar) return to zero signals of the appropriate programmable shape. the unipolar data is provided by the digital transmitter. figure 26 transmitter configuration (e1) similar to the receive line interface three different data types are supported: ternary signal single-rail data is converted into a ternary signal which is output on pins xl1 and xl2. the hdb3 and ami line code is employed. selected by fmr0.xc1/0 and lim1.drs = 0. dual-rail data pcm(+), pcm(?) at multifunction ports xdop/xdon with 50% or 100% duty cycle and with programmable polarity. line coding is done in the same way as in ternary interface mode. selected by fmr0.xc1/0 and lim1.drs = 1. unipolar data on port xoid is transmitted either in nrz (non return to zero) with 100% duty cycle or in cmi (code mark inversion or known as 1t2b) code with or without (fmr3.cmi) preprocessed hdb3 coding to a fiber-optical interface. clocking off data is done with the rising edge of the transmit clock xclk (2048 khz) and with a programmable polarity. selection is done by fmr0.xc1 = 0 and lim1.drs = 1. table 22 recommended transmitter configuration values (e1) parameter characteristic impedance [ ? ] 120 75 r 1 ( 1%) [ ? ]7.5 1) 1) this value refers to an ideal transformer without any parasitics. any transformer resistance or other parasitic resistances have to be taken into account when calculating the final value of the output serial resistors. 7.5 1) t2 : t1 1 : 2.4 1 : 2.4 f56v2_transmitter_1 xl1 xl2 r 1 line t 2 t 1 r 1 falc ? 56 pef 2256 h/e functional description e1 user?s manual 99 ds1.1, 2003-10-23 hardware description 4.4.3 transmit jitter attenuator (e1) the transmit jitter attenuator dco-x circuitry generates a "jitter-free" transmit clock and meets the following requirements: itu-t i.431, g. 703, g. 736 to 739, g.823 and etsi tbr12/13. the dco-x circuitry works internally with the same high frequency clock as the receive jitter attenuator. it synchronizes either to the working clock of the transmit backplane interface or the clock provided on pin tclk or the receive clock rclk (remote loop/loop-timed). the dco-x attenuates the incoming clock jitter starting at 2 hz with 20 db per decade fall-off. with the jitter attenuated clock, which is directly depending on the phase difference of the incoming clock and the jitter attenuated clock, data is read from the transmit elastic buffer (2 frames) or from the jatt buffer (2 frames, remote loop). wander with a jitter frequency below 2 hz is passed transparently. the dco-x accepts gapped clocks which are used in atm or sdh/sonet applications. the jitter attenuated clock is output on pin xclk or optionally on pin clk2. in case of missing clock on pin sclkx the dco-x centers automatically, if selected by bit cmr2.dcoxc = 1. the transmit jitter attenuator can be disabled. in that case data is read from the transmit elastic buffer with the clock sourced on pin tclk (2.048 or 8.192 mhz). synchronization between sclkx and tclk has to be done externally. in the loop-timed clock configuration (lim2.elt) the dco-x circuitry generates a transmit clock which is frequency synchronized on rclk. in this configuration the transmit elastic buffer has to be enabled. falc ? 56 pef 2256 h/e functional description e1 user?s manual 100 ds1.1, 2003-10-23 hardware description figure 27 transmit clock system (e1) note: dr = dual-rail interface dco-x digital controlled oscillator transmit 4.4.4 transmit elastic buffer (e1) the received bit stream from pin xdi is optionally stored in the transmit elastic buffer. the memory is organized as the receive elastic buffer. the functions are also equal to the receive side. programming of the transmit buffer size is done by sic1.xbs1/0: xbs1/0 = 00: bypass of the transmit elastic buffer xbs1/0 = 01: one frame buffer or 256 bits maximum of wander amplitude (peak-to-peak): 100 ui (1 ui = 488 ns) average delay after performing a slip: 128 bits xbs1/0 = 10: two frame buffer or 512 bits maximum of wander amplitude: 190 ui average delay after performing a slip: 1 frame or 256 bits xbs1/0 = 11: short buffer or 92 bits: maximum of wander amplitude: 18 s average delay after performing a slip: 46 bits the functions of the transmit buffer are: its10305 pulse shaper d jitter framer sclkx xl1/ xdop/ xl2/ xdon xclk a xoid dr dr elastic store xdi rclk tclk transmit attenuator dco-x sclkr internal clock of receive system tclk 4 clocking unit mclk (e1: 8mhz) interface transmit (t1: 6mhz) e1: 8mhz t1: 6mhz falc ? 56 pef 2256 h/e functional description e1 user?s manual 101 ds1.1, 2003-10-23 hardware description clock adaption between system clock (sclkx) and internally generated transmit route clock (xclk). compensation of input wander and jitter. frame alignment between system frame and transmit route frame reporting and controlling of slips writing of received data from xdi is controlled by sclkx/r and sypx /xmfs in combination with the programmed offset values for the transmit time slot/clock slot counters. reading of stored data is controlled by the clock generated by dco-x circuitry or the externally generated tclk and the tr ansmit framer. with the de-jittered clock data is read from the transmit elastic buffer and are forwarded to the transmitter. reporting and controlling of slips is done according to the receive direction. positive/negative slips are reported in interrupt status bits isr4.xsp and isr4.xsn. if the transmit buffer is bypassed data is directly transferred to the transmitter. the following table gives an overview of the transmit buffer operating modes. 4.4.5 programmable pulse shaper (e1) the analog transmitter includes a programmable pulse shaper to satisfy the requirements of itu-t i.431. the amplitude and shape of the transmit pulses are completely programmable by registers xpm(2:0). the transmitter requires an external st ep up transformer to drive the line. note: to achieve higher slew rates the pulse undershoot can be programmed in the 3 rd and 4 th sub pulse fraction by setting lim2.eou and the corresponding bits in registers xpm (2:0). 4.4.6 transmit line monitor (e1) the transmit line monitor compares the transmit line current on xl1 and xl2 with an on-chip transmit line current limiter. the monitor detects faults on the primary side of the transformer indicated by a highly increased transmit line current (more than 120 ma for at least 3 consecutive pulses sourced by v ddx 1) ) and protects the device from damage by setting the transmit line driver xl1/2 into high-impedance state automatically (if enabled by xpm2.daxlt = 0). the current limiter checks the actual current value of table 23 transmit buffer operating modes (e1) sic1.xbs(1:0) buffer size ts offset programming slip performance 00 bypass enabled no 11 short buffer enabled yes 01 1 frame enabled yes 10 2 frames enabled yes falc ? 56 pef 2256 h/e functional description e1 user?s manual 102 ds1.1, 2003-10-23 hardware description xl1/2 and if the transmit line current drops below the detection limit the high-impedance state is cleared. two conditions are detected by the monitor: transmit line de-jitteredity (more than 31 consecutive zeros) indicated by frs1.xlo and transmit line high current indicated by frs1.xls. in both cases a transmit line monitor status change interrupt is provided. figure 28 transmit line monitor configuration (e1) 4.4.7 transmit signaling controller (e1) similar to the receive signaling controller the same signaling methods and the same time slot assignment is provided. the falc ? 56 performs the following signaling and data link methods. 4.4.7.1 hdlc or lapd access the transmit signaling controller of the falc ? 56 performs the flag generation, crc generation, zero-bit stuffing and programmable idle code generation. buffering of transmit data is done in the 64 byte deep xfifo. the signaling information is internally multiplexed with the data applied to port xdi or xsig. in signaling controller transparent mode, fully transparent data transmission without hdlc framing is performed. optionally the falc ? 56 supports the continuous transmission of the xfifo contents. the falc ? 56 offers the flexibility to insert data during certain time slots. any combinations of time slots can be programmed separately for the receive and transmit direction if using hdlc channel 1. hdlc channel 2 and 3 support one programmable time slot common for receive and transmit direction each. 1) shorts between xl1 or xl2 and v ddx are not detected its10936 pulse shaper monitor line tri xdata xl1 xl2 falc ? 56 pef 2256 h/e functional description e1 user?s manual 103 ds1.1, 2003-10-23 hardware description each hdlc controller can be used to operate on the line side (called "normal hdlc") or on the system side (called "inverse hdlc"). 4.4.7.2 support of signaling system #7 the hdlc controller of channel 1 supports the signaling system #7 (ss7) which is described in itu-q.703. the following description assumes, that the reader is familiar with the ss7 protocol definition. ss7 support must be activated by setting the mode register. data stored in the transmit fifo (xfifo) is sent automatically. the ss7 protocol is supported by the following hardware features in transmit direction: transmission of flags at the beginning of each signaling unit bit stuffing (zero insertion) calculation of the crc16 checksum: the transmitter adds the checksum to each signaling unit. each signaling unit written to the transmit fifo (xfifo, 2 32 bytes) is sent once or repeatedly including flags, crc checksum and stuffed bits. after e.g. an msu has been transmitted completely, the falc ? 56 optionally starts sending of fisus containing the forward sequence number (fsn) and the backward sequence number (bsn) of the previously transmitted signaling unit. setting bit ccr5.afx causes fill in signaling units (fisus) to be sent continuously, if no hdlc or signaling unit (su) is to be transmitted from xfifo. during update of xfifo, automatic transmission is interrupted and resumed after update is completed. the internally generated fisus contain fsn and bsn of the last transmitted signaling unit written to xfifo. using cmdr.xrep = 1, the contents of xfifo can be sent continuously. clearing of cmdr.xres/sres stops the automatic repetition of transmission. this function is also available for hdlc frames, so no flag generation, crc byte generation and bit stuffing is necessary. example: after an msu has been sent repetitively and xrep has been cleared, fisus are sent automatically. 4.4.7.3 s a -bit access (e1) the falc ? 56 supports the s a -bit signaling of time slot 0 of every other frame as follows: the access through register xsw the access through registers xsa(8:4), capable of storing the information for a complete multiframe the access through the 64 byte deep xfifo of the signaling controller (hdlc channel 1 only) this s a -bit access gives the opportunity to transparent a bit stream as well as hdlc frames where the signaling controller automatically processes the hdlc protocol. any falc ? 56 pef 2256 h/e functional description e1 user?s manual 104 ds1.1, 2003-10-23 hardware description combination of s a -bits which shall be inserted in the outgoing data stream can be selected by xc0.sa(8:4). 4.4.7.4 channel associated signaling cas (e1, serial mode) in external signaling mode (serial mode) the signaling data received on port xsig is sampled with the working clock of the transmit system interface (sclkx) in combination with the transmit synchronization pulse (sypx ). data on xsig is latched in the bit positions 5 to 8 per time slot, bits 1 to 4 are ignored. time slots 0 and 16 are sampled completely (bit 1 to 8). the received cas multiframe is inserted frame aligned into the data stream on xdi and must be valid during the last frame of a multiframe if crc4/multiframe mode is selected. the cas multiframe is aligned to the crc4-multiframe; other frames are ignored. data sourced by the internal signaling controller (p access mode) overwrites the external signaling data. if the falc ? 56 is configured for no signaling, the system interface data stream passes the falc ? 56 undisturbedly. note: cas data on xsig is read in the last frame of a multiframe only and ignored in all other frames. figure 29 2.048 mhz transmit signaling highway (e1) 4.4.7.5 channel associated signaling cas (e1, p access mode) transmit data stored in registers xs(16:1) is transmitted on a multiframe boundary in time slot 16. the signaling controller inserts the bit stream either on the transmit line side or, if external signaling is enabled, on the transmit system side using pin function xsig. data sourced by the internal signaling controller overwrites the external signaling data. f0132 a b c d a b c d 4 5 6 7 0 1 2 3 4 5 6 7 ts31 ts0 ts1 0 0 0 0 x y x x 0 1 2 3 4 5 6 7 ts16 a b c d 0 1 2 3 4 5 6 7 ts31 xsig xdi sclkx fas/nfas fas/nfas sypx t 125 s t = time slot offset (xc0, xc1) fas = frame alignment signal, is taken from xsig, not from xdi nfas = ts0 not containing fas abcd = signaling bits for time slots 1...15 and 17...31 of cas multiframe 0000xyxx = cas multiframe alignment signal, has to be provided in ts16 falc ? 56 pef 2256 h/e functional description e1 user?s manual 105 ds1.1, 2003-10-23 hardware description if the falc ? 56 is configured for no signaling, the system interface data stream passes the falc ? 56 undisturbedly. 4.5 system interface in e1 mode the falc ? 56 offers a flexible feature for system designers where for transmit and receive direction different system clocks and system pulses are necessary. the interface to the receive system highway is realized by two data buses, one for the data rdo and one for the signaling data rsig. the receive highway is clocked on pin sclkr, while the interface to the transmit system highway is independently clocked on pin sclkx. the frequency of these working clocks and the data rate of 2.048/4.096/8.192/16.384 mbit/s for the receive and transmit system interface is programmable by sic1.ssc1/0, and sic1.ssd1, fmr1.ssd0. selectable system clock and data rates and their valid combinations are shown in the table below = valid, - = invalid generally the data or marker on the system interface are clocked off or latched on the rising or falling edge (sic3.resr/x) of the sclkr/x clock. some clocking rates allow transmission of time slots in different channel phases. each channel phase which shall be active on ports rdo, xdi, rp(a:d) and xp(a:d) is programmable by sic2.sics(2:0), the remaining channel phases are cleared or ignored. the signals on pin sypr together with the assigned time slot offset in register rc0 and rc1 define the beginning of a frame on the receive system highway.the signal on pin sypx or xmfs together with the assigned time slot offset in register xc0 and xc1 define the beginning of a frame on the transmit system highway. adjusting the frame begin (time slot 0, bit 0) relative to sypr/x or xmfs is possible in the range of 0 to 125 s. the minimum shift of varying the time slot 0 begin can be programmed between 1 bit and 1/8 bit depending of the system clocking and data rate, e.g. with a clocking/data rate of 2.048 mhz shifting is done bit by bit, while running the falc ? 56 with 16.384 mhz and 2.048 mbit/s data rate it is done by 1/8 bit. a receive frame marker rfm can be activated during any bit position of the entire frame. programming is done with registers rc1/0. the pin function rfm is selected by table 24 system clocking and data rates (e1) system data rate clock rate 2.048 mhz clock rate 4.096 mhz clock rate 8.192 mhz clock rate 16.384 mhz 2.048 mbit/s 4.096 mbit/s - 8.192 mbit/s - - 16.384 mbit/s - - - falc ? 56 pef 2256 h/e functional description e1 user?s manual 106 ds1.1, 2003-10-23 hardware description pc(4:1).rpc(2:0) = 001. the rfm selection disables the internal time slot assigner, no offset programming is performed. the receive frame marker is active high for one 2.048 mhz cycle or one system clock cycle (see gpc1.srfm) and is clocked off with the rising or falling edge of the clock which is in/output on port sclkr (see sic3.resr/x). compared to the receive path the inverse functions are performed for the transmit direction. the interface to the transmit system highway is realized by two data buses, one for the data xdi and one for the signaling data xsig. the time slot assignment is equivalent to the receive direction. latching of data is controlled by the system clock (sclkx) and the synchronization pulse (sypx /xmfs) in combination with the programmed offset values for the transmit time slot/clock slot counters xc1/0. the frequency of the working clock of 2.048/4.096/8.192/16.384 mhz for the transmit system interface is programmable by sic1.ssc1/0. refer also to table 24 . the received bit stream on ports xdi and xsig can be multiplexed internally on a time slot basis, if enabled by sic3.ttrf = 1. the data received on port xsig can be sampled if the transmit signaling marker xsigm is active high. data on port xdi is sampled if xsigm is low for the corresponding time slot. programming the xsigm marker is done with registers ttr(4:1). falc ? 56 pef 2256 h/e functional description e1 user?s manual 107 ds1.1, 2003-10-23 hardware description figure 30 system interface (e1) f56v2_system_interface receive signaling buffer receive elastic buffer receive backplane receive jitter attenuator transmit signaling buffer transmit elastic buffer transmit backplane transmit jitter attenuator rsigm rsig rmfb rfm dlr freeze rfsp sclkr dco-r rp(a...d) dco-r sypr rdo sclkx xp(a...d) xdi rclk tclk dco-r receive data receive clock transmit data transmit clock plb byp byp xsig sypx xmfs tclk xsigm xmfb dlx xclk xlt 1 0 1 0 los gpi gpi falc ? 56 pef 2256 h/e functional description e1 user?s manual 108 ds1.1, 2003-10-23 hardware description 4.5.1 receive system interface (e1) figure 31 receive system interface clocking (e1) itd10951 ~ ~ ~ ~ frame 1 frame 2 frame 3 frame 15 frame 16 frame 1 frame 2 frame 15 ~ ~ ~ ~~ ~ ~ ~ ~ ~ bit 255 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 2 bit 1 bit 0 bit 255 t multi frame 1 multi frame 2 4 mbit interface 2 mbit interface programmable via rc0/1 rdo rmfb sypr sypr sclkr 8.192 mhz 2.048 mhz sclkr 2 mbit/s data rate rdo/rsig ts0 rdo/rsig (sclkr = 8.192 mhz) 4 mbit/s data rate dlr sa-bit marker xc0 . sa8e-sa4e receive frame marker rfm rc0/1 rsigm time-slot marker rtr1...4 4 mbit/s data rate (sclkr = 8.192 mhz) rdo/rsig trigger edge edge sample marks any sa bit bit position marks any marks any time-slot 4 mbit interface 2 mbit interface bit 3 bit 4 bit 5 bit 6 bit 7 1) only falling trigger edge shown, depending on bit sic3.resr 1) falc ? 56 pef 2256 h/e functional description e1 user?s manual 109 ds1.1, 2003-10-23 hardware description 4.5.1.1 receive offset programming depending on the selection of the synchronization signals (sypr or rfm), different calculation formulas are used to define the position of the synchronization pulses. these formulas are given below, see figure 32 to figure 35 for explanation. the pulse length of sypr and rfm is always the basic e1 bit width (488 ns), independent of the selected system highway clock and data frequency. sypr offset calculation t: time between beginning of sypr pulse and beginning of next frame (time slot 0, bit 0), measured in number of sclkr clock intervals maximum delay: t max =(256 sc/sd)-1 sd: basic data rate; 2.048 mbit/s sc: system clock rate; 2.048, 4.096, 8.192, or 16.384 mhz x: programming value to be written to registers rc0 and rc1 (see page 249 ). 0 t 4: x = 4 - t 5 t t max : x = 2052 - t rfm offset calculation mp: marker position of rfm, counting in sclkr clock cycles (0 = bit 1, time slot 0, channel phase 0) sc = 2.048 mhz: 0 mp 255 sc = 4.096 mhz: 0 mp 511 sc = 8.192 mhz: 0 mp 1023 sc = 16.384 mhz: 0 mp 2047 sd: basic data rate; 2.048 mbit/s sc: system clock rate; 2.048, 4.096, 8.192, or 16.384 mhz x: programming value to be written to registers rc0 and rc1 (see page 249 ). 0 mp 2045: x = mp + 2 2046 mp 2047: x = mp - 2046 falc ? 56 pef 2256 h/e functional description e1 user?s manual 110 ds1.1, 2003-10-23 hardware description figure 32 sypr offset programming (2.048 mbit/s, 2.048 mhz) figure 33 sypr offset programming (8.192 mbit/s, 8.192 mhz) f0221a 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 rdo 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 ts0 ts1 ts31 ts0 ts1 sypr sclkr sic3.resr = 0 (falling edge) sclkr sic3.resr = 1 (rising edge) t = 0 sypr t t sypr 256 - t f0221b sypr sclkr sic3.resr = 0 (falling edge) sclkr sic3.resr = 1 (rising edge) t = 0 sypr t t sypr sc/sd x 256 - t rdo (cp0) (ts = time slot, cp = channel phase) 1 2 3 4 ts31-cp3 5 6 7 8 ts0 - cp0 ts0 - cp1 1 2 3 4 5 6 7 8 ts0 - cp0 ts0 - cp1 rdo (cp1) 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 rdo (cp3) 1 2 3 4 5 6 7 8 falc ? 56 pef 2256 h/e functional description e1 user?s manual 111 ds1.1, 2003-10-23 hardware description figure 34 rfm offset programming (2.048 mbit/s, 2.048 mhz) figure 35 rfm offset programming (8.192 mbit/s, 8.192 mhz) f0221c 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 rdo 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 ts0 ts1 ts31 ts0 ts1 rfm sclkr sic3.resr = 0 (falling edge) sclkr sic3.resr = 1 (rising edge) bp = 0 rfm rfm bp = 12 bp = 251 f0221d rdo (cp0) sclkr sic3.resr = 0 (falling edge) sclkr sic3.resr = 1 (rising edge) byte-interleaved (ts = time slot, cp = channel phase) 1 2 3 4 ts31-cp3 rfm bp = 0 rfm rfm bp = 12 bp = 1020 5 6 7 8 ts0 - cp0 ts0 - cp1 1 2 3 4 5 6 7 8 ts0 - cp0 ts0 - cp1 rdo (cp1) 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 rdo (cp3) 1 2 3 4 5 6 7 8 falc ? 56 pef 2256 h/e functional description e1 user?s manual 112 ds1.1, 2003-10-23 hardware description 4.5.2 transmit system interface (e1) figure 36 transmit system interface clocking: 2.048 mhz (e1) frame0 frame1 frame2 frame15 frame0 frame1 frame2 multi frame 1 multi frame 2 xdi xmfb xmfs sypx trigger edge 1) bit 0 sample edge 1) sclkx xdi/xsig bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 dlx sa-bit marker xc0.sa8e-sa4e bit 4 marked 1) only falling edge mode shown 2) delay t is programmable by xc0/1; sypx t 2) xsigm ts0 f0003 falc ? 56 pef 2256 h/e functional description e1 user?s manual 113 ds1.1, 2003-10-23 hardware description figure 37 transmit system interface clocking: 8.192 mhz/4.096 mbit/s (e1) frame0 frame1 frame2 frame15 frame0 frame1 frame2 multi frame 1 multi frame 2 xdi xmfb xmfs sypx trigger edge 1) bit 0 sample edge 1) sclkx xdi/xsig 3) sic2.sics2-0=000 dlx sa-bit marker xc0.sa8e-sa4e sic2.sics2-0=000 bit 4 marked 1) only falling edge mode shown 2) delay t is programmable by xc0/1; 3) data 4.096 mbit/s, clock 8.192 mhz sypx t 2) 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 bit 4 marked dlx sa-bit marker xc0.sa8e-sa4e sic2.sics2-0=000 xdi/xsig 3) sic2.sics2-0=001 xsigm time-slot marker ttr1...4 sic2.sics2-0=000 f0004 falc ? 56 pef 2256 h/e functional description e1 user?s manual 114 ds1.1, 2003-10-23 hardware description 4.5.2.1 transmit offset programming the pulse length of sypx is always the basic e1 bit width (488 ns), independent of the selected system highway clock and data frequency. sypx offset calculation t: time between beginning of sypx pulse and beginning of next frame (time slot 0, bit 0), measured in number of sclkx clock intervals maximum delay: t max =(256 sc/sd)-1 sd: basic data rate; 2.048 mbit/s sc: system clock rate; 2.048, 4.096, 8.192, or 16.384 mhz x: programming value to be written to registers xc0 and xc1 (see page 247 ). 0 t 4: x = 4 - t 5 t t max : x = 256 sc/sd - t + 4 falc ? 56 pef 2256 h/e functional description e1 user?s manual 115 ds1.1, 2003-10-23 hardware description figure 38 sypx offset programming (2.048 mbit/s, 2.048 mhz) figure 39 sypx offset programming (8.192 mbit/s, 8.192 mhz) f0223a 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 xdi 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 ts0 ts1 ts31 ts0 ts1 sypx sclkx sic3.resx = 1 (rising edge) sclkx sic3.resx = 0 (falling edge) t = 0 sypx t t sypx 256 - t f0223b sypx sclkx sic3.resx = 1 (rising edge) sclkx sic3.resx = 0 (falling edge) t = 0 sypx t t sypx sc/sd x 256 - t xdi (cp0) (ts = time slot, cp = channel phase) 1 2 3 4 ts31-cp3 5 6 7 8 ts0 - cp0 ts0 - cp1 1 2 3 4 5 6 7 8 ts0 - cp0 ts0 - cp1 xdi (cp1) 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 xdi (cp3) 1 2 3 4 5 6 7 8 falc ? 56 pef 2256 h/e functional description e1 user?s manual 116 ds1.1, 2003-10-23 hardware description 4.5.3 time slot assigner (e1) hdlc channel 1 offers the flexibility to connect data during certain time slots, as defined by registers rtr(4:1) and ttr(4:1), to the rfifo and xfifo, respectively. any combinations of time slots can be programmed for the receive and transmit directions. if ccr1.eits = 1 the selected time slots (rtr(4:1)) are stored in the rfifo of the signaling controller and the xfifo contents is inserted into the transmit path as controlled by registers ttr(4:1). for hdlc channels 2 and 3, one out of 31 time slots can be selected for each channel, but in common for transmit and receive direction. within selected time slots single bit positions can be masked to be used/not used for hdlc transmission for all hdlc channels. additionally, the use of even, odd or both frames can be selected for each hdlc channel individually. table 25 time slot assigner hdlc channel 1 (e1) receive time slot register transmit time slot register time slot receive time slot register transmit time slot register time slot rtr 1.7 ttr 1.7 0 rtr 3.7 ttr 3.7 16 rtr 1.6 ttr 1.6 1 rtr 3.6 ttr 3.6 17 rtr 1.5 ttr 1.5 2 rtr 3.5 ttr 3.5 18 rtr 1.4 ttr 1.4 3 rtr 3.4 ttr 3.4 19 rtr 1.3 ttr 1.3 4 rtr 3.3 ttr 3.3 20 rtr 1.2 ttr 1.2 5 rtr 3.2 ttr 3.2 21 rtr 1.1 ttr 1.1 6 rtr 3.1 ttr 3.1 22 rtr 1.0 ttr 1.0 7 rtr 3.0 ttr 3.0 23 rtr 2.7 ttr 2.7 8 rtr 4.7 ttr 4.7 24 rtr 2.6 ttr 2.6 9 rtr 4.6 ttr 4.6 25 rtr 2.5 ttr 2.5 10 rtr 4.5 ttr 4.5 26 rtr 2.4 ttr 2.4 11 rtr 4.4 ttr 4.4 27 rtr 2.3 ttr 2.3 12 rtr 4.3 ttr 4.3 28 rtr 2.2 ttr 2.2 13 rtr 4.2 ttr 4.2 29 rtr 2.1 ttr 2.1 14 rtr 4.1 ttr 4.1 30 rtr 2.0 ttr 2.0 15 rtr 4.0 ttr 4.0 31 falc ? 56 pef 2256 h/e functional description e1 user?s manual 117 ds1.1, 2003-10-23 hardware description 4.6 test functions (e1) 4.6.1 pseudo-random binary sequence generation and monitor the falc ? 56 has the ability to generate and monitor 2 15 -1 and 2 20 -1 pseudo-random binary sequences (prbs). the generated prbs pattern is transmitted to the remote end on pins xl1/2 or xdop/n and can be inverted optionally. generating and monitoring of prbs pattern is done according to itu-t o.151. the prbs monitor senses the prbs pattern in the incoming data stream. synchronization is done on the inverted and non-inverted prbs pattern. the current synchronization status is reported in status and interrupt status registers. enabled by bit lcr1.eprm each prbs bit error increments an error counter (cec2). synchronization is reached within 400 ms with a probability of 99.9% at a bit error rate of up to 10 -1 . the prbs generator and monitor can be used to handle either a framed (tpc0.fra = 1) or an unframed (tpc0.fra = 0) data stream. 4.6.2 remote loop in the remote loop-back mode the clock and data recovered from the line inputs rl1/2 or rdip/rdin are routed back to the line outputs xl1/2 or xdop/xdon through the analog or digital transmitter. as in normal mode they are also processed by the synchronizer and then sent to the system interface. the remote loop-back mode is selected by setting the corresponding control bits lim1.rl and lim1.jatt. received data can be looped with or without the transmit jitter attenuator (fifo). figure 40 remote loop (e1) its09750 rdo xdi rclk rl1 rl2 xl1 xl2 fifo xclk rclk dco-r/x framer rec. framer trans. store elast. elast. store recovery data clock + mux mux falc ? 56 pef 2256 h/e functional description e1 user?s manual 118 ds1.1, 2003-10-23 hardware description 4.6.3 payload loop-back to perform an effective circuit test a payload loop is implemented. the payload loop-back (fmr2.plb) loops the data stream from the receiver section back to transmitter section. the looped data passes the complete receiver including the wander and jitter compensation in the receive elastic store and is output on pin rdo. instead of the data an ais signal (fmr2.sais) can be sent to the system interface. the framing bits, crc4 and spare bits are not looped, if xsp.tt0 = 0. they are generated by the falc ? 56 transmitter. if the plb is enabled the transmitter and the data on pins xl1/2 or xdop/xdon are clocked with sclkr instead of sclkx. if xsp.tt0 = 1 the received time slot 0 is sent back transparently to the line interface. data on the following pins is ignored: xdi, xsig, sclkx, sypx and xmfs. all the received data is processed normally. figure 41 payload loop (e1) its09748 clock + data rec. framer elast. store trans. framer rdo xdi rclk rl1 rl2 xl1 xl2 recovery sclkx sclkr mux ais-gen elast. store falc ? 56 pef 2256 h/e functional description e1 user?s manual 119 ds1.1, 2003-10-23 hardware description 4.6.4 local loop the local loop-back mode selected by lim0.ll = 1 disconnects the receive lines rl1/2 or rdip/rdin from the receiver. instead of the signals coming from the line the data provided by the system interface is routed through the analog receiver back to the system interface. however, the bit stream is transmitted undisturbedly on the line. however, an ais to the distant end can be enabled by setting fmr1.xais = 1 without influencing the data looped back to the system interface. note that enabling the local loop usually invokes an out-of-frame error until the receiver resynchronizes to the new framing. the serial codes for transmitter and receiver have to be identical. figure 42 local loop (e1) its09749 rdo xdi rclk ais-gen rl1 rl2 xl1 xl2 framer rec. framer trans. store elast. recovery data clock + mux elast. store falc ? 56 pef 2256 h/e functional description e1 user?s manual 120 ds1.1, 2003-10-23 hardware description 4.6.5 single channel loop-back each of the 32 time slots can be selected for loop-back from the system pcm input (xdi) to the system pcm output (rdo). this loop-back is programmed for one time slot at a time selected by register loop. during loop-back, an idle channel code programmed in register idle is transmitted to the remote end in the corresponding pcm route time slot. for the time slot test, sending sequences of test patterns like a 1-khz check signal shall be avoided. otherwise an increased occurrence of slips in the tested time slot disturbs testing. these slips do not influence the other time slots and the function of the receive memory. the usage of a quasi-static test pattern is recommended. figure 43 single channel loop-back (e1) its09747 rdo xdi rclk rl1 rl2 xl1 xl2 idle code framer trans. framer rec. store elast. store elast. mux mux recovery data clock + falc ? 56 pef 2256 h/e functional description e1 user?s manual 121 ds1.1, 2003-10-23 hardware description 4.6.6 alarm simulation (e1) alarm simulation does not affect the normal operation of the device, i.e. all time slots remain available for transmission. however, possible real alarm conditions are not reported to the processor or to the remote end when the device is in the alarm simulation mode. the alarm simulation is initiated by setting the bit fmr0.sim. the following alarms are simulated: loss-of-signal (los) alarm indication signal (ais) loss of pulse frame remote alarm indication receive and transmit slip indication framing error counter code violation counter (hdb3 code) crc4 error counter e-bit error counter cec2 counter cec3 counter some of the above indications are only simulated if the falc ? 56 is configured to a mode where the alarm is applicable (e.g. no crc4 error simulation when doubleframe format is enabled). setting of the bit fmr0.sim initiates alarm simulation, interrupt status bits are set. error counting and indication occurs while this bit is set. after it is reset all simulated error conditions disappear, but the generated interrupt statuses are still pending until the corresponding interrupt status register is read. alarms like ais and los are cleared automatically. interrupt status registers and error counters are automatically cleared on read. 4.6.7 single bit defect insertion single bit defects can be inserted into the transmit data stream for the following functions: fas defect, multiframe defect, crc defect, cas defect, prbs defect and bipolar violation. defect insertion is controlled by register ierr. falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 122 ds1.1, 2003-10-23 hardware description 5 functional description t1/j1 5.1 receive path in t1/j1 mode figure 44 receive clock system (t1/j1) 5.1.1 receive line interface (t1/j1) for data input, three different data types are supported: ternary coded signals received at multifunction ports rl1 and rl2 from a -36 db ternary interface. the ternary interface is selected if lim1.drs is reset. digital dual-rail signals received on ports rdip and rdin. the dual-rail interface is selected if lim1.drs and fmr0.rc1 is set. unipolar data on port roid received from a fiber-optical interface. the optical interface is selected if lim1.drs is set and fmr0.rc1 is reset. 5.1.2 receive short and long -haul interface (t1/j1) the falc ? 56 has an integrated short-haul and long-haul line interface, including a receive equalization network, noise filtering and programmable line build-outs (lbo). equalizer clock & data recovery dpll line decoder alarm detector anal og los detector rdata rclk sync rl1/rdip/roid rl2/rdin/rclki dco-r receive jitter attenuator mc lk fsc receive system interface f0117 falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 123 ds1.1, 2003-10-23 hardware description 5.1.3 receive equalization network (t1/j1) the falc ? 56 automatically recovers the signals received on pins rl1/2. the maximum reachable length with a 22 awg twisted-pair cable is 2000 m (~6560 ft.). the integrated receive equalization network recovers signals with up to -36 db of cable attenuation in long-haul mode. noise filters eliminate the higher frequency part of the received signals. the incoming data is peak-detected and sliced to produce the digital data stream. the slicing level is software selectable in four steps (45%, 50%, 55%, 67%). the received data is then forwarded to the clock and data recovery unit. the receive equalizer characteristics are programmable to enable the use of non-standard cable types or to adapt to special receive conditions. 5.1.4 receive line attenuation indication (t1/j1) status register res reports the current receive line attenuation in a range from 0 to -36 db in 25 steps of approximately 1.4 db each. the least significant 5 bits of this register indicate the cable attenuation in db. these 5 bits are only valid in combination with the most significant two bits (res.ev1/0 = 01). 5.1.5 receive clock and data recovery (t1/j1) the analog received signal on port rl1/2 is equalized and then peak-detected to produce a digital signal. the digital received signal on port rdip/n is directly forwarded to the dpll. the receive clock and data recovery extracts the route clock rclk from the data stream received at the rl1/2, rdip/rdin or roid lines and converts the data stream into a single-rail, unipolar bit stream. the clock and data recovery uses an internally generated high frequency clock based on mclk. the recovered route clock or a de-jittered clock can be output on pin rclk as shown in table 26 . see also table 29 on page 130 for details of master/slave clocking. falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 124 ds1.1, 2003-10-23 hardware description the intrinsic jitter generated in the absence of any input jitter is not more than 0.035 ui. in digital bipolar line interface mode the clock and data recovery requires hdb3 coded signals with 50% duty cycle. 5.1.6 receive line coding (t1/j1) the b8zs line code or the ami (zcs, zero code suppression) coding is provided for the data received from the ternary or the dual rail interface. all code violations that do not correspond to zero substitution rules are detected. if a bit error causes a code violation that leads to a valid substitution pattern, this code violation is not detected and the substitution pattern is replaced by the corresponding zero pattern. the detected errors increment the 16-bit code violation counter. in case of the optical interface a selection between the nrz code and the cmi code (1t2b) with b8zs or ami postprocessing is provided. if cmi code is selected the receive route clock is recovered from the data stream. the cmi decoder does not correct any errors. in case of nrz coding data is latched with the falling edge rclki. when using the optical interface with nrz coding, the decoder is bypassed and no code violations are detected. additionally, the receive line interface contains the alarm detection for alarm indication signal ais (blue alarm) and the loss-of-signal los (red alarm). table 26 rclk output selection (t1/j1) clock source rclk frequency cmr1. dcs cmr1. rs1/0 sic2. ssc2 receive data (1.544 mbit/s on rl1/rl2, rdip/rdin or roid) 1.544 mhz 00 receive data in case of los constant high 01 1.544 mhz (generated by dco-r, synchronized on sync) 1101 dco-r 1.544 mhz 10 1 2.048 mhz 10 0 6.176 mhz 11 1 8.192 mhz 11 0 falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 125 ds1.1, 2003-10-23 hardware description 5.1.7 receive line termination (t1/j1) the signal at the ternary interface is received at both ends of a transformer. a termination resistor is used to achieve line impedance matching (see figure 45 and table 27 ). figure 45 receiver configuration (t1/j1) table 27 recommended receiver configuration values (t1/j1) line impedance external resistor r 2 transformer ratio t 2 :t 1 120 ? 120 ? 1) 1) this includes all parasitic effects caused by circuit board design. 1 : 1 110 ? 110 ? 1) 1 : 1 f56v2_receiver_ 5 rl1 rl2 r 2 line t 2 t 1 falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 126 ds1.1, 2003-10-23 hardware description 5.1.8 receive line monitoring mode for short-haul applications like shown in figure 46 , the receive equalizer can be switched into receive line monitoring mode (lim0.rlm = 1). one device is used as a short-haul receiver while the other is used as a short-haul monitor. in this mode the receiver sensitivity is increased to detect an incoming signal of -20 db resistive attenuation. the required resistor values are given in table 28 . figure 46 receive line monitoring using the receive line monitor mode and the hardware tristate function of transmit lines xl1/2, the falc ? 56 now supports applications connecting two devices to one receive and transmission line. in these kind of applications both devices are working in parallel table 28 external component recommendations (monitoring) parameter 1) 1) this includes all parasitic effects caused by circuit board design. characteristic impedance [ ? ] t1 j1 r 1 ( 1 %) [ ? ] 100 110 r 2 ( 1 %) [ ? ] 100 110 r 3 ( 1 %) [ ? ] 430 470 t 2 : t 1 1 : 1 1 : 1 f56v2_receiver_ 4 receiver monitor rl1 e1/t1/j1 receive line lim0.rlm=0 lim0.rlm=1 r1 r2 r3 r3 rl2 rl1 rl2 t2 : t1 t2 : t1 resistive - 20 db network falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 127 ds1.1, 2003-10-23 hardware description for redundancy purpose (see figure 47 ). while one of them is driving the line, the other one must be switched into transmit line tristate mode. if both channels are configured identically and supplied with the same system data and clocks, the transmit path can be switched from one channel to the other without causing a synchronization loss at the remote end. due to the use of the receive line monitor mode, this setup is limited to short haul applications. switching between both devices can be done through the microcontroller interface or by using the tristate hardware input pin as shown in the figure. figure 47 protection switching application (t1/j1) for long haul redundancy requirements (see figure 48 ), the analog switches can be used to enable the line termination for the active device and to disable it for the stand-by part. switching between both devices is controled through the microcontroller interface. f56v2_receiver_2 e1/t1/j1 receive line rl1 rl2 rdo rl1 rl2 rdo xl1 xl2 e1/t1/j1 transmit line xdi xl1 xl2 xdi trist trist 1 active device stand-by device falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 128 ds1.1, 2003-10-23 hardware description figure 48 long haul protection switching application (t1/j1) 5.1.9 loss-of-signal detection (t1/j1) there are different definitions for detecting loss-of-signal alarms (los) in the itu-t g.775 and at&t tr 54016. the falc ? 56 covers all these standards. the los indication is performed by generating an interrupt (if not masked) and activating a status bit. additionally a los status change interrupt is programmable by register gcr.sci. detection: an alarm is generated if the incoming data stream has no pulses (no transitions) for a certain number (n) of consecutive pulse periods. ?no pulse? in the digital receive interface means a logical zero on pins rdip/rdin or roid. a pulse with an amplitude less than q db below nominal is the criteria for ?no pulse? in the analog receive interface (lim1.drs = 0). the receive signal level q is programmable by f56v2_receiver_ 3 e1/t1/j1 receive line rl1 rl2 rdo rl1 rl2 rdo xl1 xl2 e1/t1/j1 transmit line xdi xl1 xl2 xdi active device stand-by device falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 129 ds1.1, 2003-10-23 hardware description three control bits lim1.ril(2:0) (see chapter 11.3 on page 466 ). the number n is set by an 8-bit register (pcd). the contents of the pcd register is multiplied by 16, which results in the number of pulse periods, i.e. the time which has to suspend until the alarm has to be detected. the programmable range is 16 to 4096 pulse periods. recovery: in general the recovery procedure starts after detecting a logical "1" (digital receive interface) or a pulse (analog receive interface) with an amplitude more than q db (defined by lim1.ril(2:0)) of the nominal pulse. the value in the 8-bit register pcr defines the number of pulses (1 to 255) to clear the los alarm. additional recovery conditions are programmed by register lim2. if a loss-of-signal condition is detected in long-haul mode, the data stream can optionally be cleared automatically to avoid bit errors before los is indicated. the selection is done by lim1.clos = 1. 5.1.10 receive jitter attenuator (t1/j1) the receive jitter attenuator is placed in the receive path. the working clock is an internally generated high frequency clock based on the clock provided on pin mclk. the jitter attenuator meets the requirements of pub 62411, pub 43802, tr-tsy 009,tr-tsy 253, tr-tsy 499 and itu-t i.431, g.703 and g. 824. the internal pll circuitry dco-r generates a "jitter-free" output clock which is directly depending on the phase difference of the incoming clock and the jitter attenuated clock.the receive jitter attenuator can be synchronized either on the extracted receive clock rclk or on a 1.544-, 2.048-mhz or 8-khz clock provided on pin sync (8 khz in master mode only). the received data is written into the receive elastic buffer with rclk and are read out with the de-jittered clock sourced by dco-r. the jitter attenuated clock can be output on pins rclk, clk1 or sclkr. optionally an 8-khz clock is provided on pin sec/fsc. the dco-r circuitry attenuates the incoming jittered clock starting at 6-hz jitter frequency with 20 db per decade fall-off. wander with a jitter frequency below 6 hz is passed unattenuated. the intrinsic jitter in the absence of any input jitter is < 0.02 ui. for some applications it might be useful to start jitter attenuation at lower frequencies. therefore the corner frequency is switchabl e by the factor of ten down to 0.6 hz (lim2.scf). the dco-r circuitry is automatically centered to the nominal bit rate if the reference clock on pin sync/rclk is missed for 2, 3 or 4 of the 2.048-mhz or 1.544-mhz clock periods. this center function of dco-r can be optionally disabled (cmr2.dcf = 1) in order to accept a gapped reference clock. in analog line interface mode the rclk is always running. only in digital line interface mode with single-rail data (nrz) a gapped clock on pin rclk can occur. the receive jitter attenuator works in two different modes: falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 130 ds1.1, 2003-10-23 hardware description slave mode in slave mode (lim0.mas = 0) the dco-r is synchronized on the recovered route clock. in case of los the dco-r switches automatically to master mode. if bit cmr1.dcs is set automatic switching from rclk to sync is disabled. master mode in master mode (lim0.mas = 1) the jitter attenuator is in free running mode if no clock is supplied on pin sync. if an external clock on the sync input is applied, the dco-r synchronizes to this input. the external frequency can be 1.544 mhz (lim1.dcoc = 0; ipc.ssyf = 0), 2.048 mhz (lim1.dcoc = 1; ipc.ssyf = 0) or 8.0 khz (ipc.ssyf = 1; lim1.dcoc = don?t care). the following table shows the clock modes with the corresponding synchronization sources. table 29 system clocking (t1/j1) mode internal los active sync input system clocks master independent fixed to v dd dco-r centered, if cmr2.dcf = 0. (cmr2.dcf should not be set) master independent 1.544 mhz synchronized on sync input (external 1.544 mhz, ipc.ssyf = 0, lim1.dcoc = 0) master independent 2.048 mhz synchronized on sync input (external 2.048 mhz, ipc.ssyf = 0, lim1.dcoc = 1) master independent 8.0 khz synchronized on sync input (external 8.0 khz, ipc.ssyf = 1, cmr2.dcf = 0) slave no fixed to v dd synchronized on line rclk slave no 1.544 or 2.048 mhz synchronized on line rclk slave yes fixed to v dd cmr1.dcs = 0: dco-r is centered, if cmr2.dcf = 0. (cmr2.dcf should not be set) cmr1.dcs = 1: synchronized on line rclk falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 131 ds1.1, 2003-10-23 hardware description the jitter attenuator meets the jitter transfer requirements of the pub 62411, pub 43802, tr-tsy 009,tr-tsy 253, tr-tsy 499 and itu-t i.431 and g.703 (refer to figure 49 ). figure 49 jitter attenuation performance (t1/j1) slave yes 1.544 or 2.048 mhz cmr1.dcs = 0: synchronized on sync input (external 1.544 or 2.048 mhz) cmr1.dcs = 1: synchronized on line clock rclk table 29 system clocking (t1/j1) (cont?d) mode internal los active sync input system clocks itd10314 1 -70 frequency attenuation -60 -50 -40 -30 -20 -10 0 10 10 100 1000 10000 100000 db hz slope slope - - 40 20 db/decade db/decade falc pub 62411_h pub 62411_l r falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 132 ds1.1, 2003-10-23 hardware description 5.1.11 jitter tolerance (t1/j1) the falc ? 56 receiver?s tolerance to input jitter complies with itu, at&t and telcordia requirements for t1 applications. figure 50 shows the curves of different input jitter specifications stated below as well as the falc ? 56 performance. figure 50 jitter tolerance (t1/j1) jitter amplitude jitter frequency 1 10 100 1000 10000 100000 hz ui 1 0.1 10 100 1000 pub 62411 tr-nwt 000499 cat ii ccitt g.823 itu-t i.431 falc ? f0025 falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 133 ds1.1, 2003-10-23 hardware description 5.1.12 output jitter (t1/j1) according to the input jitter defined by pub62411 the falc ? 56 generates the output jitter which is specified in table 30 below. 5.1.13 framer/synchronizer (t1/j1) the following functions are performed: synchronization on pulse frame and multiframe error indication when synchronization is lost. in this case, ais is sent to the system side automatically and remote alarm to the remote end if enabled. initiating and controlling of resynchronization after reaching the asynchronous state. this is done automatically by the falc ? 56 or user controlled by the microprocessor interface. detection of remote alarm (yellow alarm) indication from the incoming data stream. separation of service bits and data link bits. this information is stored in special status registers. detection of framed or unframed in-band loop-up/-down code generation of various maskable interrupt statuses of the receiver functions. generation of control signals to synchronize the crc checker, and the receive elastic buffer. if programmed and applicable to the selected multiframe format, crc checking of the incoming data stream is done by generating check bits for a crc multiframe according to the crc6 procedure (as defined in itu-t g.704). these bits are compared with those check bits that are received during the next crc multiframe. if there is at least one mismatch, the 16-bit crc error counter is incremented. 5.1.14 receive elastic buffer (t1/j1) the received bit stream is stored in the receive elastic buffer. the memory is organized as a two-frame elastic buffer with a maximum size of 2 193 bit. the size of the elastic buffer is configured independently for the receive and transmit direction. programming of the receive buffer size is done by sic1.rbs1/0: table 30 output jitter (t1/j1) specification measurement filter bandwidth output jitter (ui peak to peak) lower cutoff upper cutoff pub 62411 10 hz 8 khz < 0.015 8 khz 40 khz < 0.015 10 hz 40 khz < 0.015 broadband < 0.02 falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 134 ds1.1, 2003-10-23 hardware description rbs1/0 = 00: two frame buffer or 386 bits maximum of wander amplitude (peak-to-peak): (1 ui = 648 ns) system interface clocking rate: modulo 2.048 mhz: 142 ui in channel translation mode 0 78 ui in channel translation mode 1 system interface clocking rate: modulo 1.544 mhz: maximum of wander: 140 ui average delay after performing a slip: 1 frame or 193 bits rbs1/0 = 01: one frame buffer or 193 bits system interface clocking rate: modulo 2.048 mhz: maximum of wander: 70 ui in channel translation mode 0 maximum of wander: 50 ui in channel translation mode 1 system interface clocking rate: modulo 1.544 mhz: maximum of wander: 74 ui average delay after performing a slip: 96 bits rbs1/0 = 10: short buffer or 96 bits system interface clocking rate: modulo 2.048 mhz: maximum of wander: 28 ui in channel translation mode 0; channel translation mode 1 not supported system interface clocking rate: modulo 1.544 mhz: maximum of wander: 38 ui average delay after performing a slip: 48 bits rbs1/0 = 11: bypass of the receive elastic buffer the buffer functions are: clock adaption between system clock (sclkr) and internally generated route clock (rclk). compensation of input wander and jitter. frame alignment between system frame and receive route frame reporting and controlling of slips controlled by special signals generated by the receiver, the unipolar bit stream is converted into bit-parallel, time slot serial da ta which is circularly written to the elastic buffer using internally generated receive route clock (rclk). reading of stored data is controlled by the system clock sourced by sclkr or by the receive jitter attenuator and the synchronization pulse (sypr ) together with the programmed offset values for the receive time slot/clock slot counters. after conversion into a serial data stream, the data is sent out on port rdo. if the receive buffer is bypassed programming of the time slot offset is disabled and data is clocked off with rclk instead of sclkr. the 24 received time slots (t1/j1) can be translated into the 32 system time slots (e1) in two different channel translation modes (fmr1.ctm). unequipped time slots are set to ff h . see table 31 . falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 135 ds1.1, 2003-10-23 hardware description ? : ff h in one frame or short buffer mode the delay through the receive buffer is reduced to an average delay of 96 or 48 bits. in bypass mode the time slot assigner is disabled. in this case sypr programmed as input is ignored. slips are performed in all buffer modes except bypass mode. after a slip is detected the read pointer is adjusted to one half of the current buffer size. table 32 gives an overview of the receive buffer operating mode. table 31 channel translation modes (ds1/j1) channels time slots channels time slots channel translation mode 0 channel translation mode 1 channel translation mode 0 channel translation mode 1 fs/dlfs/dl0?1616 111131717 222141818 333151919 ? 44?2020 455162121 566172222 677182323 ? 88?2424 79919?25 8 101020? 26 9 111121? 27 ?1212??28 10 13 13 22 ? 29 11 14 14 23 ? 30 12 15 15 24 ? 31 falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 136 ds1.1, 2003-10-23 hardware description figure 51 gives an idea of operation of the receive elastic buffer: a slip condition is detected when the write pointer (w) and the read pointer (r) of the memory are nearly coincident, i.e. the read pointer is within the slip limits (s +, s ?). if a slip condition is detected, a negative slip (one frame or one half of the current buffer size is skipped) or a positive slip (one frame or one half of the current buffer size is read out twice) is performed at the system interface, depending on the difference between rclk and the current working clock of the receive backplane interface, i.e. on the position of pointer r and w within the memory. a positive/negative slip is indicated by the interrupt status bits isr3.rsp and isr3.rsn. table 32 receive buffer operation modes (t1/j1) buffer size (sic1.rbs1/0) ts offset program. (rc1/0) + sypr = input slip perform. bypass 1) 1) in bypass mode the clock provided on pin sclkr is ignored. clocking is done with rclk. disabled no short buffer not recommended, recommended: sypr = output yes 1 frame not recommended, recommended: sypr = output yes 2 frames enabled yes falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 137 ds1.1, 2003-10-23 hardware description figure 51 the receive elastic buffer as circularly organized memory limits for slip detection (mode dependent) read pointer (system clock controlled) write pointer (route clock controlled) r? s+, s- r : : w: frame 2 time slots s- r frame 1 time slots moment of slip detection itd10952 w s+ slip falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 138 ds1.1, 2003-10-23 hardware description 5.1.15 receive signaling controller (t1/j1) the signaling controller can be programmed to operate in various signaling modes. the falc ? 56 performs the following signaling and data link methods. 5.1.15.1 hdlc or lapd access the falc ? 56 offers three independent hdlc channels. any hdlc channel can be attached either to the line side ("normal hdlc") or to the system side ("inverse hdlc"). each of them provides the following features: 64 byte receive fifo for each channel 64 byte transmit fifo for each channel transmission in one of 24 time slots (time slot number programmable for each channel individually) transmission in even frames only, odd frames only or both (programmable for each channel individually) bit positions to be used in selected time slots are maskable (any bit position can be enabled for each channel individually) hdlc or transparent mode flag detection crc checking bit-stuffing flexible address recognition (1 byte, 2 bytes) c/r bit processing (according to lapd protocol) in addition to this, hdlc channel 1 provides: ss7 support bom (bit oriented message) support flexibility to insert and extract data during certain time slots, any combination of time slots can be programmed independently for the receive and transmit direction in case of common channel signaling the signaling procedure hdlc/sdlc or lapd according to q.921 is supported. the signaling controller of the falc ? 56 performs the flag detection, crc checking, address comparison and zero bit removing. the received data flow and the address recognition features can be performed in very flexible way, to satisfy almost any practical requirements. depending on the selected address mode, the falc ? 56 performs a 1 or 2-byte address recognition. if a 2-byte address field is selected, the high address byte is compared with the fixed value feh or fch (group address) as well as with two individually programmable values in rah1 and rah2 registers. according to the isdn lapd protocol, bit 1 of the high byte address is interpreted as command/response bit (c/r) and is excluded from the address comparison. buffering of receive data is done in a 64 byte deep rfifo. in signaling controller transparent mode, fully transparent data reception without hdlc framing is performed, i.e. without flag recognition, crc checking or bit stuffing. this allows user specific protocol variations. falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 139 ds1.1, 2003-10-23 hardware description 5.1.15.2 support of signaling system #7 the hdlc controller of channel 1 supports the signaling system #7 (ss7) which is described in itu-q.703. the following description assumes, that the reader is familiar with the ss7 protocol definition. ss7 support must be activated by setting the mode register. the ss7 protocol is supported by the following hardware features in receive mode: all signaling units (su) are stored in the receive fifo (rfifo) detecting of flags from the incoming data stream bit stuffing (zero deletion) checking of seven or more consecutive ones in the receive data stream checking if the received signaling unit is a multiple of eight bits and at least six octets including the opening flag calculation of the crc16 checksum: in receive direction the calculated checksum is compared to the received one; errors are reported in register rsis. checking if the signal information field of a received signaling unit consists of more than 272 octets, in this case the current signaling unit is discarded. in order to reduce the microprocessor load, fill in signaling units (fisus) are processed automatically. by examining the length indicator of a received signal unit the falc ? 56 decides whether a fisu has been received. consecutively received fisus are compared and optionally not stored in the receive fifo (rfifo, 2 32 bytes), if the contents is equal to the previous one. the same applies to link status signaling units, if bit ccr5.csf is set. the different types of signaling units as message signaling unit (msu), link status signaling unit (lssu) and fill in signaling units (fisu) are indicated in the rsis register, which is automatically added to the rfifo with each received signaling unit. the complete signaling unit except start and end flags is stored in the receive fifo. the functions of bits ccr1.rcrc and ccr1.radd are still valid in ss7 mode. errored signaling units are handled automatically according to itu-t q.703 as shown in figure 23 . su counter (su) and errored su counter (c s ) are reset by setting cmdr2.rsuc. the error threshold t can be selected to be 64 (default) or 32 by setting/clearing bit ccr5.suet. if the defined error limit is exceeded, an interrupt (isr1.suex) is generated, if not masked by imr1.suex = 1. note: if suex is caused by an aborted/invalid frame, the interrupt will be issued regularly until a valid frame is received (e.g. a fisu). falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 140 ds1.1, 2003-10-23 hardware description figure 52 automatic handling of errored signaling units reset counter values c s := 0 su := 0 [cmdr2.rsuc = 1] idle in service su in error? c s := c s + 1 su := su + 1 su := su + 1 c s = t ? su = 256 ? su := 0 c s = 0 ? c s := c s -1 in service link failure [isr1.suex = 1] idle notes : su: signaling units counter c s : errored signaling units counter t: error threshold (64 or 32), selectable by ccr5.suet n n n n y y y y f0071 falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 141 ds1.1, 2003-10-23 hardware description 5.1.15.3 cas bit-robbing (t1/j1, serial mode) the signaling information is carried in the lsb of every sixth frame for each time slot. the signaling controller samples the bit stream either on the receive line side or if external signaling is enabled on the receive system side on port rsig. receive signaling data is stored in the registers rs(12:1). optionally the complete cas multiframe is transmitted on pin rsig (fmr5.eibr = 1). the signaling data is clocked out with the working clock of the receive highway (sclkr) together with the receive synchronization pulse (sypr ). data on rsig is transmitted in the last 4 bits per time slot and are time slot aligned to the data on rdo. in esf format the a, b, c, and d bits are placed in bit positions 5 to 8 of each time slot. in f12/72 format the a and b bits are repeated in the c and d bit positions. the first 4 bits per time slot can be optionally fixed high or low. the fs/dl time slot is transmitted on rdo and rsig. during idle time slots no signaling information is transmitted. data on rsig are only valid if the freeze signaling status is inactive. with fmr2.sais all-ones data is transmitted on rdo and rsig. robbed bits can be forced to one on rdo for all channels or only for those that are not selected as "cleared channels". updating of the received signaling information is controlled by the freeze signaling status. the freeze signaling status is automatically activated if a loss-of-signal, or a loss-of-frame-alignment or a receive slip occurs. the current freeze status is output on port freeze (rp(a:d)) and indicated by register sis.sfs. if sis.sfs is active updating of the registers rs(12:1) is disabled. optionally automatic freeze signaling is disabled by setting bit sic3.daf. after cas resynchronization an interrupt is generated. because at this time the signaling is still frozen, cas data is not valid yet. read out of cas data has to be delayed until the next cas multiframe is received. 5.1.15.4 cas bit-robbing (t1/j1, p access mode) the signaling information is carried in the lsb of every sixth frame for each time slot. receive data is stored in registers rs(12:1) aligned to the cas multiframe boundary. to relieve the p load from always reading the complete rs(12:1) buffer every 3 ms the falc ? 56 notifies the p by interrupt isr0.rsc only when signaling changes from one multiframe to the next. this interrupt can be suppressed for "cleared channels" (ccr1.rscc = 1). additionally the falc ? 56 generates a receive signaling data change pointer (rsp1/2) which directly points to the updated rs(12:1) register. because the cas controller is working on the pcm highway side of the receive buffer, slips disturb the cas data. 5.1.15.5 bit oriented messages in esf-dl channel (t1/j1) the falc ? 56 hdlc channel 1 supports the dl-channel protocol for esf format according to ansi t1.403 specification or according to at&t tr54016. the hdlc and falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 142 ds1.1, 2003-10-23 hardware description bit oriented message (bom) receiver are switched on/off independently. if the falc ? 56 is used for hdlc formats only, the bom receiver has to be switched off. if hdlc and bom receiver have been switched on (mode.hrac/brac), an automatic switching between hdlc and bom mode is enabled. if eight or more consecutive ones are detected, the bom mode is entered. upon detection of a flag in the data stream, the falc ? 56 switches back to hdlc mode. in bom mode, the following byte format is assumed (the left most bit is received first): 111111110xxxxxx0 three different bom reception modes can be programmed (ccr1.brm+ ccr2.rbfe). if ccr2.rfbe is set, the bom receiver accepts only bom frames after detecting 7 out of 10 equal bom pattern. buffering of receive data is done in a 64 byte deep rfifo. 5.1.15.6 4 kbit/s data link access in f72 format (t1/j1) the dl-channel protocol is supported as follows: access is done on a multiframe basis through registers rdl(3:1), the dl-bit information from frame 26 to 72 is stored in the receive fifo of the signaling controller. 5.2 framer operating modes (t1/j1) 5.2.1 general activated with bit fmr1.pmod = 1. pcm line bit rate : 1.544 mbit/s single frame length : 193 bit, no. 1?193 framing frequency : 8 khz organization : 24 time slots, no. 1?24 with 8 bits each, no. 1?8 and one preceding f-bit selection of one of the four permissible framing formats is performed by bits fmr4.fm1/0. these formats are: f4 : 4-frame multiframe f12 : 12-frame multiframe (d4) esf : extended superframe (f24) f72 : 72-frame multiframe (slc96) the operating mode of the falc ? 56 is selected by programming the carrier data rate and characteristics, line code, multiframe structure, and signaling scheme. the falc ? 56 implements all of the standard and/or common framing structures pcm24 (t1/j1, 1.544 mbit/s) carriers. the internal hdlc controller supports all signaling procedures including signaling frame synchronization/synthesis in all framing formats. falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 143 ds1.1, 2003-10-23 hardware description after reset, the falc ? 56 must be programmed with fmr1.pmod = 1 to enable the t1/j1 (pcm24) mode. switching between the framing formats is done by bit fmr4.fm1 ? 0 for the receiver and for the transmitter. 5.2.2 general aspects of synchronization synchronization status is reported by bit frs0.lfa (loss of frame alignment). framing errors (pulse frame and multiframe) are counted by the framing error counter fec. asynchronous state is reached if 2 out of 4 (bit fmr4.ssc1/0 = 00), or 2 out of 5 (bit fmr4.ssc1/0 = 01), or 2 out of 6 (bit fmr4.ssc1/0 = 10), or 4 consecutive multiframe pattern in esf format are incorrect (bit fmr4.ssc1/0 = 11). if auto mode is enabled, counting of framing errors is interrupted. the resynchronization procedure is controlled by either one of the following procedures: automatically (fmr4.auto = 1). additionally, it can be triggered by the user by setting/resetting one of the bits fmr0.frs (force resynchronization) or fmr0.exls (external loss of frame). user controlled, exclusively, by the control bits described above in the non-auto mode (fmr4.auto = 0). 5.2.3 addition for f12 and f72 format ft and fs bit conditions, i.e. pulse frame alignment and multiframe alignment can be handled separately if programmed by bit fmr2.ssp. thus, a multiframe resynchronization can be automatically initiated after detecting 2 errors out of 4/5/6 consecutive multiframing bits without influencing the state of the terminal framing. in the synchronous state, the setting of fmr0.frs or fmr0.exls resets the synchronizer and initiates a new frame search. the synchronous state is reached if there is only one definite framing candidate. in the case of repeated apparent simulated candidates, the synchronizer remains in the asynchronous state. in asynchronous state, the function of fmr0.exls is the same as above. setting bit fmr0.frs induces the synchronizer to lock onto the next available framing candidate if there is one. otherwise a new frame search is started. this is useful in case the framing pattern that defines the pulseframe position is imitated periodically by a pattern in one of the speech/data channels. the control bit fmr0.exls should be used first because it starts the synchronizer to search for a definite framing candidate. to observe actions of the synchronizer, the frame search restart flag frs0.fsrf is implemented. it toggles at the start of a new frame search if no candidate has been found at previous attempt. falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 144 ds1.1, 2003-10-23 hardware description when resynchronization is initiated, the following values apply for the time required to achieve the synchronous state in case there is one definite framing candidate within the data stream: table 33 resynchronization timing (t1/j1) frame mode average maximum units f4 f12 esf f72 1.0 3.5 3.4 13.0 1.5 4.5 6.125 17.75 ms falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 145 ds1.1, 2003-10-23 hardware description figure 53 influences on synchronization status (t1/j1) itd03574 auto-mode definite candidate synchronous asynchronous exls frs don doff synchronous asynchronous non-auto-mode definite candidate exls, frs don doff exls, frs synchronous multiple candidates asynchronous multiple candidates synchronous asynchronous exls, frs frs don doff exls frs 1) exls, frs frs don doff exls frs 1) : depends on the disturbance d one disturbance : falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 146 ds1.1, 2003-10-23 hardware description figure 53 gives an overview of influences on synchronization status for the case of different external actions. activation of auto mode and non-auto mode is performed by bit fmr4.auto. generally, for initiating resynchronization it is recommended to use bit: fmr0.exls first. in cases where the synchronizer remains in the asynchronous state, bit fmr0.frs is used to enforce it to lock onto the next framing candidate, although it might be a simulated one. 5.2.4 4-frame multiframe (f4 format, t1/j1) the allocation of the ft-bits (bit 1 of frames 1 and 3) for frame alignment signal is shown in table 34 . the fs-bit can be used for signaling. remote alarm (yellow alarm) is indicated by setting bit 2 to 0 in each time slot. 5.2.4.1 synchronization procedure for multiframe synchronization, the terminal framing bits (ft-bits) are observed. the synchronous state is reached if at least one terminal framing candidate is definitely found, or the synchronizer is forced to lock onto the next available candidate (fmr0.frs). table 34 4-frame multiframe structure (t1/j1) frame number f t f s 11 2?service bit 30 4?service bit falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 147 ds1.1, 2003-10-23 hardware description 5.2.5 12-frame multiframe (d4 or sf format, t1/j1) normally, this kind of multiframe structure only makes sense when using the cas robbed-bit signaling. the multiframe alignment signal is located at the fs-bit position of every other frame (refer to table 35 ). there are two possibilities of remote alarm (yellow alarm) indication: bit 2 = 0 in each time slot of a frame, selected with bit fmr0.sraf = 0 the last bit of the multiframe alignment signal (bit 1 of frame 12) changes from "0" to "1", selected with bit fmr0.sraf = 1. 5.2.5.1 synchronization procedure in the synchronous state terminal framing (ft-bits) and multiframing (fs-bits) are observed, independently. further reaction on framing errors depends on the selected synchronization/resynchronization procedure (by bit fmr2.ssp): fmr2.ssp = 0: terminal frame and multiframe synchronization are combined. two errors within 4/5/6 framing bits (by bits fmr4.ssc1/0) of one of the above leads to the asynchronous state for terminal framing and multiframing. additionally to the bit frs0.lfa, loss of multiframe alignment is reported by bit frs0.lmfa. the resynchronization procedure starts with synchronizing upon the terminal framing. if the pulse framing has been regained, the search for multiframe alignment table 35 12-frame multiframe structure (t1/j1) frame number f t f s signaling channel designation 11? 2?0 30? 4?0 51? 6 ?1a 70? 8?1 91? 10 ? 1 11 0 ? 12?0b falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 148 ds1.1, 2003-10-23 hardware description is initiated. multiframe synchronization has been regained after two consecutive correct multiframe patterns have been received. fmr2.ssp = 1: terminal frame and multiframe synchronization are separated two errors within 4/5/6 terminal framing bits lead to the same reaction as described above for the ?combined? mode. two errors within 4/5/6 multiframing bits lead to the asynchronous state only for the multiframing. loss of multiframe alignment is reported by bit frs0.lmfa. the state of terminal framing is not influenced. now, the resynchronization procedure includes only the search for multiframe alignment. multiframe synchronization has been regained after two consecutive correct multiframe patterns have been received. if multiple framing candidates exist in the received data, setting bit fmr2.afrs enables automatic search for the valid framing. 5.2.6 extended superframe (f24 or esf format, t1/j1) the use of the first bit of each frame for the multiframe alignment word, the data link bits, and the crc bits is shown in table 36 on page 148 . table 36 extended superframe structure (f24, esf; t1/j1) multiframe frame number f-bits signaling channel designation multiframe bit number assignments fas dl crc 10?m? 2193??e 1 3386?m? 45790?? 5772?m? 6965??e 2 a 71158?m? 813510?? 91544?m? 10 1737 ? ? e 3 11 1930 ? m ? 12 2123 1 ? ? b 13 2316 ? m ? 14 2509 ? ? e 4 falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 149 ds1.1, 2003-10-23 hardware description 5.2.6.1 synchronization procedures for multiframe synchronization the fas-bits are observed. synchronous state is reached if at least one framing candidate is definitely found, or the synchronizer is forced to lock onto the next available candidate (fmr0.frs). in the synchronous state the framing bits (fas-bits) are observed. the following conditions selected by fmr4.ssc1/0 lead to the asynchronous state: two errors within 4/5/6 framing bits two or more erroneous framing bits within one esf multiframe more than 320 crc6 errors per second interval (fmr5.ssc2) 4 incorrect (1 out of 6) consecutive multiframes independent of crc6 errors. there are four multiframe synchronization modes selectable using fmr2.mcsp and fmr2.ssp. fmr2.mcsp/ssp = 00: in the synchronous state, the setting of fmr0.frs or fmr0.exls resets the synchronizer and initiates a new frame search. the synchronous state is reached again, if there is only one definite framing candidate. in the case of repeated apparent simulated candidates, the synchronizer remains in the asynchronous state. in asynchronous state, setting bit fmr0.frs induces the synchronizer to lock onto the next available framing candidate if there is one. at the same time the internal framing pattern memory is cleared and other possible framing candidates are lost. fmr2.mcsp/ssp = 01: synchronization is achieved when 3 consecutive multiframe pattern are correctly found independent of the occurrence of crc6 errors. if only one 15 2702 ? m ? 16 2895 0 ? ? 17 3088 ? m ? 18 3231 ? ? e 5 c 19 3474 ? m ? 20 3667 1 ? ? 21 3860 ? m ? 22 4053 ? ? e 6 23 4246 ? m ? 24 4439 1 ? ? d table 36 extended superframe structure (f24, esf; t1/j1) (cont?d) multiframe frame number f-bits signaling channel designation multiframe bit number assignments fas dl crc falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 150 ds1.1, 2003-10-23 hardware description or two consecutive multiframe pattern were detected the falc ? 56 stays in the asynchronous state, searching for a possible additionally available framing pattern. this procedure is repeated until the framer has found three consecutive multiframe pattern in a row. fmr2.mcsp/ssp = 10: this mode has been added in order to be able to choose multiple framing pattern candidates step by step. i.e. if in synchronous state the crc error counter indicates that the synchronization might have been based on an alias framing pattern, setting of fmr0.frs leads to synchronization on the next candidate available. however, only the previously assumed candidate is discarded in the internal framing pattern memory. the latter procedure can be repeated until the framer has locked on the right pattern (no extensive crc errors). the synchronizer is reset completely and initiates a new frame search, if there is no multiframing found. in this case bit frs0.fsrf toggles. fmr2.mcsp/ssp = 11: synchronization including automatic crc6 checking synchronization is achieved when framing pattern are correctly found and the crc6 checksum is received without an error. if the crc6 check failed on the assumed framing pattern the falc ? 56 stays in the asynchronous state, searching for a possible available framing pattern. this procedure is repeated until the framer has locked on the right pattern. this automatic synchronization mode has been added in order to reduce the microprocessor load. 5.2.6.2 remote alarm (yellow alarm) generation/detection remote alarm (yellow alarm) is indicated by the periodical pattern "1111 1111 0000 0000 ?" in the dl-bits (t1 mode, rc0.sjr = 0). remote alarm is declared even in the presence of a bit error rate of up to 10 -3 . the alarm is reset when the yellow alarm pattern no longer is detected. depending on bit rc0.sjr = 1 the falc ? 56 generates and detects the remote alarm according to jt g. 704. in the dl-bit position 16 continuous "1" are transmitted if fmr0.sraf = 0 and fmr4.xra = 1. 5.2.6.3 crc6 generation and checking (t1/j1) generation and checking of crc6 bits transmitted/received in the e(6:1) bit positions is done according to itu-t g.706. the crc6 checking algorithm is enabled by bit fmr1.crc. if not enabled, all check bits in the transmit direction are set. in the synchronous state received crc6 errors are accumulated in a 16 bit error counter and are additionally indicated by an interrupt status. crc6 inversion if enabled by bit rc0.crci, all crc bits of one outgoing extended multiframe are automatically inverted in case a crc error is flagged for the previous received multiframe. setting the bit rc0.xcrci inverts the crc bits before transmitted to the distant end. this function is logically ored with rc0.crci. falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 151 ds1.1, 2003-10-23 hardware description crc6 generation/checking according to jt g.706 setting of rc0.sjr the falc ? 56 generates and checks the crc6 bits according to jt g.706. the crc6 checksum is calculated including the fs/dl-bits. in synchronous state crc6 errors increment an error counter. 5.2.7 72-frame multiframe (slc96 format, t1/j1) the 72-multiframe is an alternate use of the fs-bit pattern and is used for carrying data link information. this is done by stealing some of redundant multiframing bits after the transmission of the 12-bit framing header (refer to figure 37 on page 152 ). the position of a and b signaling channels (robbed bit signaling) is defined by zero-to-one and one-to-zero transitions of the fs-bits and is continued when the fs-bits are replaced by the data link bits. remote alarm (yellow alarm) is indicated by setting bit 2 to zero in each time slot. an additional use of the d-bits for alarm indication is user defined and must be done externally. 5.2.7.1 synchronization procedure in the synchronous state terminal framing (ft-bits) and multiframing (fs-bits of the framing header) are observed independently. further reaction on framing errors depends on the selected synchronization/resynchronization procedure (by bit fmr2.ssp): fmr2.ssp = 0: terminal frame and multiframe synchronization are combined two errors within 4/5/6 framing bits (by bits fmr4.ssc1/0) of one of the above lead to the asynchronous state for terminal framing and multiframing. additionally to the resynchronization procedure starts with synchronizing upon the terminal framing. if the pulse framing has been regained, the search for multiframe alignment is initiated. multiframe synchronization has been regained after two consecutive correct multiframe patterns have been received. fmr2.ssp = 1: terminal frame and multiframe synchronization are separated two errors within 4/5/6 terminal framing bits lead to the same reaction as described above for the ?combined? mode. two errors within 4/5/6 multiframing bits lead to the asynchronous state only for the multiframing. loss of multiframe alignment is reported by bit frs0.lmfa. the state of terminal framing is not influenced. now, the resynchronization procedure includes only the search for multiframe alignment. multiframe synchronization has been regained after two consecutive correct multiframe patterns have been received. falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 152 ds1.1, 2003-10-23 hardware description table 37 72-frame multiframe structure (t1/j1) frame number f t f s signaling channel designation 11? 2?0 30? 4?0 51? 6 ?1a 70? 8?1 91? 10 ? 1 11 0 ? 12?0b 13 1 ? 14 ? 0 15 0 ? 16 ? 0 17 1 ? 18?1a 19 0 ? 20 ? 1 21 1 ? 22 ? 1 23 0 ? 24 ? d b 25 ? ? 26 1 d 27 ? ? 28 0 d ... ... ... ... falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 153 ds1.1, 2003-10-23 hardware description 66 ? d a 67 0 ? 68 ? d 69 1 ? 70 ? d 71 0 ? 72 table 37 72-frame multiframe structure (t1/j1) (cont?d) frame number f t f s signaling channel designation falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 154 ds1.1, 2003-10-23 hardware description 5.2.8 summary of frame conditions (t1/j1) table 38 summary frame recover/out of frame conditions (t1/j1) format frame recover condition out of frame condition f4 only one ft pattern found, optional forcing on next available ft framing candidate 2 out of 4/5/6 incorrect ft-bits f12 (d4) and f72 (slc96) fmr2.ssp = 0: combined ft + fs framing search: first searching for ft pattern with optional forcing on next available framing candidates and then for 2 consecutive correct fs pattern 1) . fmr2.ssp = 1: separated ft + fs pattern search: loss of ft framing starts first search for ft and then for 2 consecutive correct fs pattern 1) . loss of fs framing starts only the fs pattern 1) search. 1) in f12 (d4) format bit 1 in frame 12 is excluded from the synchronization process. fmr2.ssp = 0: 2 out of 4/5/6 incorrect ft- or fs-bits fmr2.ssp = 1: 2 out of 4/5/6 incorrect ft-bits searched in ft and fs framing bits, 2 out of 4/5/6 incorrect fs-bits searched only the fs framing. f24 (esf) fmr2.mcsp/ssp = 00: only one fas pattern found, optional forcing on next available fas framing candidate with discarding of all remaining framing candidates. fmr2.mcsp/ssp = 01: 3 consecutive correct multiframing found independent of crc6 errors. fmr2.mcsp/ssp = 10: choosing multiple framing pattern step by step, optional forcing on next available fas framing pattern with discarding only of the previous assumed framing candidate. fmr2.mcsp/ssp = 11: fas framing correctly found and crc6 check error free. 2 out of 4/5 incorrect fas-bits or 2 out of 6 incorrect fas-bits per multiframe or 4 consecutive incorrect multiframing pattern or more than 320 crc6 errors per second interval falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 155 ds1.1, 2003-10-23 hardware description 5.3 additional receive framer functions (t1/j1) 5.3.1 error performance monitoring and alarm handling alarm indication signal: detection and recovery is flagged by bit frs0.ais and isr2.ais. transmission is enabled by bit fmr1.xais. loss-of-signal: detection and recovery is flagged by bit frs0.los and isr2.los. remote alarm indication: detection and release is flagged by bit frs0.rra and isr2.ra/rar. transmission is enabled by bit fmr4.xra. excessive zeros: detection is flagged by bit frs1.exzd. pulse-density violation: detection is flagged by bit frs1.pden and isr0.pden. transmit line shorted: detection and release is flagged by bit frs1.xls and isr1.xlsc. transmit ones-density: detection and release is flagged by bit frs1.xlo and isr1.xlsc. table 39 summary of alarm detection and release (t1/j1) alarm detection condition clear condition red alarm or loss-of-signal (los) no transitions (logical zeros) in a programmable time interval of 16 to 4096 consecutive pulse periods. programmable receive input signal threshold programmable number of ones (1 to 256) in a programmable time interval of 16 to 4096 consecutive pulse periods. a one is a signal with a level above the programmed threshold. or the pulse-density is fulfilled and no more than 15 contiguous zeros during the recovery interval are detected. blue alarm or alarm indication signal (ais) fmr4.ais3 = 0: less than 3 zeros in 12 frames or 24 frames (esf), fmr4.ais3 = 1: less than 4 zeros in 12 frames or less than 6 zeros in 24 frames (esf) active for at least one multiframe. fmr4.ais3 = 0: more than 2 zeros in 12 or 24 frames (esf), fmr4.ais3 = 1: more than 3 zeros in 12 frames or more than 5 zeros in 24 frames (esf) falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 156 ds1.1, 2003-10-23 hardware description 5.3.2 auto modes automatic remote alarm (yellow alarm) access if the receiver has lost its synchronization (frs0.lfa) a remote alarm (yellow alarm) is sent to the distant end automatically, if enabled by bit fmr2.axra. in synchronous state the remote alarm bit is removed. automatic ais to system interface in asynchronous state the synchronizer enforces an ais to the receive system yellow alarm or remote alarm (rra) 1) rc1.rram = 0: bit 2 = 0 in 255 consecutive time slots or fs-bit = 1 of frame12 in f12 (d4) format or 8 1,8 0 in the dl channel (esf) rc1.rram = 1: bit 2 = 0 in every time slot per frame or fs-bit = 1 of frame12 in f12 (d4) format or 8 1,8 0 in the dl channel (esf) rc1.rram = 0: set conditions no longer detected. rc1.rram = 1: bit 2 = 0 not detected in 3 consecutive frames or fs-bit not detected in 3 consecutive multiframes or 8 1,8 0 not detected for 3 times in a row (esf). excessive zeros (exzd) more than 7 (b8zs code) or more than 15 (ami code) contiguous zeros latched status: cleared on read pulse-density violation (pden) less than n ones in each and every time window of 8 (n+1) time slots with n taking all values of 1 to 23 or more than 15 consecutive zeros latched status: cleared on read transmit line short (xls) more than 3 pulse periods with highly increased transmit line current on xl1/2 transmit line current limiter inactive transmit ones-density (xlo) 32 consecutive zeros in the transmit data stream on xl1/2 cleared with each transmitted pulse 1) rra detection operates in the presence of 10 -3 bit error rate. table 39 summary of alarm detection and release (t1/j1) (cont?d) alarm detection condition clear condition falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 157 ds1.1, 2003-10-23 hardware description interface automatically. however, received data is switched through transparently if bit fmr2.dais is set. automatic clock source switching in slave mode (lim0.mas = 0) the dco-r synchronizes on the recovered route clock. in case of loss-of-signal (los) the dco-r switches to master mode automatically. if bit cmr1.dcs is set, automatic switching from rclk to sync is disabled. automatic freeze signaling: updating of the received signaling information is controlled by the freeze signaling status. the freeze signaling status is activated automatically, if a loss-of-signal or a loss of multiframe alignment or a receive slip occurs. the internal signaling buffer rs(12:1) is frozen. optionally automatic freeze signaling is disabled by setting bit sic3.daf = 1. 5.3.3 error counters the falc ? 56 offers six error counters where each of them has a length of 16 bit. they record code violations, framing bit errors, crc6 bit errors, errored blocks and the number of received multiframes in asynchronous state or the changes of frame alignment (cofa). counting of the multiframes in asynchronous state and of the cofa parameter is done in a 6/2-bit counter. each of the error counters is buffered. buffer update is done in two modes: one-second accumulation on demand using handshake with writing to the dec register. in the one-second mode an internal/external one-second timer updates these buffers and resets the counter to accumulate the error events in the next one-second period. the error counter cannot overflow. error events occurring during error counter reset are not be lost. 5.3.4 errored second the falc ? 56 supports the error performance monitoring by detecting the following alarms or error events in the received data: framing errors, crc errors, code violations, loss of frame alignment, loss-of-signal, alarm indication signal, receive and transmit slips. with a programmable interrupt mask register esm all these alarms or error events can generate an errored second interrupt (isr3.es) if enabled. 5.3.5 one-second timer additionally a one-second timer interrupt can be generated internally to indicate that the enabled alarm status bits or the error counters have to be checked. the one-second timer signal is output on port sec/fsc (gpc1.csfp1/0). optionally synchronization to falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 158 ds1.1, 2003-10-23 hardware description an external second timer is possible which has to be provided on pin sec/fsc. selecting the external second timer is done with gcr.ses. refer also to register gpc1 for input/output selection. 5.3.6 clear channel capability for support of common t1 applications, clear channels can be specified through the 3-byte register bank ccb(1:3). in this mode the contents of selected transmit time slots are not overwritten by internally or externally sourced bit-robbing and zero code suppression (b7 stuffing) information. 5.3.7 in-band loop generation and detection the falc ? 56 generates and detects a framed or unframed in-band loop-up (activate, 00001) and loop-down (deactivate, 001) pattern according to ansi t1.403 with bit error rates as high as 10 -2 . framed or unframed in-band loop code is selected by lcr1.fllb. replacing the in-band loop codes with transmit data is done by fmr5.xld/xlu. the falc ? 56 also offers the ability generating and detecting of a flexible in-band loop-up and -down pattern (lcr1.llbp = 1). the loop-up and loop-down pattern is individually programmable from 2 to 8 bits in length (lcr1.lac1/0 and lcr1.ldc1/0). programming of loop codes is done in registers lcr2 and lcr3. status and interrupt status bits inform the user whether loop-up or loop-down code was detected. 5.3.8 transparent mode the transparent modes are useful for loop-backs or for routing data unchanged through the falc ? 56. in receive direction, transparency for ternary or dual-/single-rail unipolar data is always achieved if the receiver is in the synchronous state. all bits in f-bit position of the incoming multiframe are forwarded to rdo and inserted in the fs/dl time slot or in the f-bit position. in asynchronous state the received data is switched through transparently if bit fmr2.dais is set. setting of bit loop.rtm disconnects control of the elastic buffer from the receiver. the elastic buffer is now in a ?free running? mode without any possibility to update the time slot assignment to a new frame position in case of resynchronization of the receiver. together with fmr2.dais this function is used to realize undisturbed transparent reception. setting bit fmr4.tm switches the falc ? 56 in transmit transparent mode: in transmit direction bit 8 of the fs/dl time slot from the system highway (xdi) is inserted in the f-bit position of the outgoing frame. for complete transparency the internal signaling controller, idle code generation, ais alarm generation, single channel and payload loop-back has to be disabled and cleared channels have to be defined by registers ccb1 3. falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 159 ds1.1, 2003-10-23 hardware description 5.3.9 pulse-density detection the falc ? 56 examines the receive data stream on the pulse-density requirement which is defined by ansi t1. 403. more than 14 consecutive zeros or less than n ones in each and every time window of 8 (n+1) data bits where n = 23 are detected. violations of these rules are indicated by setting the status bit frs1.pden and the interrupt status bit isr0.pden. generation of the interrupt status is programmed either with the detection or with any change of state of the pulse-density alarm (gcr.sci). 5.4 transmit path in t1/j1 mode 5.4.1 transmitter (t1/j1) the serial bit stream is then processed by the transmitter which has the following functions: frame/multiframe synthesis of one of the four selectable framing formats insertion of service and data link information ais generation (blue alarm) remote alarm (yellow alarm) generation crc generation and insertion of crc bits crc bits inversion in case of a previously received crc error or in case of activating per control bit generation of loop-up/-down code idle code generation per ds0 the frame/multiframe boundaries of the tr ansmitter can be synchronized externally by using the sypx /xmfs pin. any change of the transmit time slot assignment subsequently produces a change of the framing bit positions on the line side. this feature is required if signaling and data link bi ts are routed through the switching network and are inserted in transmit direction by the system interface. in loop-timed configuration (lim2.elt) disconnecting the control of the transmit system highway from the transmitter is done by setting fmr5.xtm. the transmitter is now in a free running mode without any possibility to update the multiframe position in case of changing the transmit time slot assignment. the fs/dl-bits are generated independent of the transmit system interface. for proper operation the transmit elastic buffer size should be programmed to 2 frames. the contents of selectable time slots is overwritten by the pattern defined by register idle. the selection of ?idle channels? is done by programming the three-byte registers icb(3:1). if ami coding with zero code suppression (b7-stuffing) is selected, ?clear channels? without b7-stuffing can be defined by programming registers ccb(3:1). falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 160 ds1.1, 2003-10-23 hardware description 5.4.2 transmit line interface (t1/j1) the analog transmitter transforms the unipolar bit stream to ternary (alternate bipolar) return to zero signals of the appropriate programmable shape. the unipolar data is provided on pin xdi and the digital transmitter. similar to the receive line interface three different data types are supported: figure 54 transmitter configuration (t1/j1) ternary signal single-rail data is converted into a ternary signal which is output on pins xl1 and xl2. selection between b8zs or simple ami coding with zero code suppression (b7 stuffing) is provided. b7 stuffing can be disabled on a per time slot basis (clear channel capability). selected by fmr0.xc1/0 and lim1.drs = 0. dual-rail data pcm(+), pcm(-) at multifunction ports xdop and xdon with 50% or 100% duty cycle and with programmable polarity. line coding is done in the same way as in ternary interface mode. selected by fmr0.xc1 = 1 and lim1.drs = 1. unipolar data on port xoid is transmitted in nrz (non return to zero) with 100% duty cycle or in cmi code with or without (sic3.cmi) preprocessed by b8zs coding to a fiber-optical interface. clocking off data is done with the rising edge of the transmit clock xclk (1544 khz) and with a programmable polarity. selection is done by fmr0.xc1 = 0 and lim1.drs = 1. table 40 recommended transmitter configuration values (t1/j1) parameter t1 j1 characteristic impedance [ ? ] 100 110 r 1 ( 1%) [ ? ]2 1) 1) this value refers to an ideal transformer without any parasitics. any transformer resistance or other parasitic resistances have to be taken into account when calculating the final value of the output serial resistors. t2 : t1 1 : 2.4 f56v2_transmitter_1 xl1 xl2 r 1 line t 2 t 1 r 1 falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 161 ds1.1, 2003-10-23 hardware description 5.4.3 transmit jitter attenuator (t1/j1) the transmit jitter attenuator dco-x circuitry generates a "jitter-free" transmit clock and meets the following requirements: pub 62411, pub 43802, tr-tsy 009,tr-tsy 253, tr-tsy 499 and itu-t i.431 and g.703. the dco-x circuitry works internally with the same high frequency clock as the receive jitter attenuator. it synchronizes either to the working clock of the transmit backplane interface or the clock provided on pin tclk or the receive clock rclk (remote loop/loop-timed). the dco-x attenuates the incoming jitter starting at 6 hz with 20 db per decade fall-off. with the jitter attenuated clock, which is directly depending on the phase difference of the incoming clock and the jitter attenuated clock, data is read from the transmit elastic buffer (2 frames) or from the jatt buffer (2 frames, remote loop). wander with a jitter frequency below 6 hz is passed transparently. the dco-x accepts gapped clocks which are used in atm or sdh/sonet applications. the jitter attenuated clock is output on pin xclk or optionally on pin clk2. in case of missing clock on pin sclkx the dco-x centers automatically, if selected by bit cmr2.dcoxc = 1. the transmit jitter attenuator can be disabled. in that case data is read from the transmit elastic buffer with the clock sourced on pin tclk (1.544 or 6.176 mhz). synchronization between sclkx and tclk has to be done externally. in the loop-timed clock configuration (lim2.elt) the dco-x circuitry generates a transmit clock which is frequency synchronized on rclk. in this configuration the transmit elastic buffer has to be enabled. falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 162 ds1.1, 2003-10-23 hardware description figure 55 clocking in remote loop configuration (t1/j1) its10299 equalizer dpll rl1/2 rdip/n roid drs line decoder receive jatt buffer rclk pulse shaper driver line drs xl1/2 xoid xdop/n line encoder data data transmit jitter attenuator transmit clock unit mclk rclk rclk ~ ~ falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 163 ds1.1, 2003-10-23 hardware description figure 56 transmit clock system (t1/j1) note: dr = dual-rail interface dco-x digital controlled oscillator transmit 5.4.4 transmit elastic buffer (t1/j1) the transmit elastic store with a size of max. 2 193 bit (two frames) serves as a temporary store for the pcm data to adapt the system clock (sclkx) to the internally generated clock for the transmit data, and to retranslate time slot structure used in the system to that of the line side. its optimal start position is initiated when programming the transmit time slot offset values. a difference in the effective data rates of system side and transmit side lead to an overflow or underflow of the transmit memory. thus, errors in data transmission to the remote end occur. th is error condition (transmit slip) is reported to the microprocessor by interrupt status registers. the received bit stream from pin xdi is optionally stored in the transmit elastic buffer. the memory is organized as the receive elastic buffer. programming of the transmit buffer size is done by sic1.xbs1/0: xbs1/0 = 00: bypass of the transmit elastic buffer xbs1/0 = 01: one frame buffer or 193 bits maximum of wander amplitude (peak-to-peak): (1 ui = 648 ns) system interface clocking rate: modulo 2.048 mhz: its10305 pulse shaper d jitter framer sclkx xl1/ xdop/ xl2/ xdon xclk a xoid dr dr elastic store xdi rclk tclk transmit attenuator dco-x sclkr internal clock of receive system tclk 4 clocking unit mclk (e1: 8mhz) interface transmit (t1: 6mhz) e1: 8mhz t1: 6mhz falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 164 ds1.1, 2003-10-23 hardware description maximum of wander: 70 ui in channel translation mode 0 maximum of wander: 45 ui in channel translation mode 1 system interface clocking rate: modulo 1.544 mhz: maximum of wander: 74 ui average delay after performing a slip: 96 bits xbs1/0 = 10: two frame buffer or 386 bits system interface clocking rate: modulo 2.048 mhz: 142 ui in channel translation mode 0 78 ui in channel translation mode 1 system interface clocking rate: modulo 1.544 mhz: maximum of wander: 140 ui average delay after performing a slip: 193 bits xbs1/0 = 11: short buffer or 96 bits: system interface clocking rate: modulo 2.048 mhz: maximum of wander: 28 ui in channel translation mode 0; channel translation mode 1 not supported system interface clocking rate: modulo 1.544 mhz: maximum of wander: 38 ui average delay after performing a slip: 48 bits the functions of the transmit buffer are: clock adaption between system clock (sclkx/r) and internally generated transmit route clock (xclk) or externally sourced tclk. compensation of input wander and jitter. frame alignment between system frame and transmit route frame reporting and controlling of slips writing of received data from xdi is controlled by sclkx/r and sypx /xmfs in combination with the programmed offset values for the transmit time slot/clock slot counters. reading of stored data is controlled by the clock generated by dco-x circuitry or the externally generated tclk and the tr ansmit framer. with the de-jittered clock data is read from the transmit elastic buffer and are forwarded to the transmitter. reporting and controlling of slips is automatically done according to the receive direction. positive/negative slips are reported in interrupt status bits isr4.xsp and isr4.xsn. a reinitialization of the transmit memory is done by reprogramming the transmit time slot counter xc1 and with the next sypx pulse. after that, this memory has its optimal start position. the frequency of the working clock for the transmit system interface is programmable by sic1.ssc1/0 and sic2.ssc2 in a range of 1.544 to 12.352 mhz/2.048 to 16.384 mhz. generally the data or marker on the system interface are clocked off or latched on the rising or falling edge (sic3.resx) of the sclkx clock. some clocking rates allow transmission of time slots/marker in different channel phases. each channel phase falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 165 ds1.1, 2003-10-23 hardware description which shall be latched on ports xdi and xp(a:d) is programmable by bits sic2.sics(2:0), the remaining channel phases are cleared or ignored respectively. the following table gives an overview of the transmit buffer operating modes. 5.4.5 programmable pulse shaper and line build-out (t1/j1) in long-haul applications the transmit pulse masks are optionally generated according to fcc68 and ansi t1. 403. to reduce the crosstalk on the received signals the falc ? 56 offers the ability to place a transmit attenuator in the data path. transmit attenuation is selectable from 0, -7.5, -15 or -22.5 db (register lim2.lbo2/1). ansi t1. 403 defines only 0 to -15 db. the falc ? 56 includes a programmable pulse shaper to satisfy the requirements of ansi t1. 102, also various ds1, dsx-1 specifications are met. the amplitude of the pulse shaper is individually programmable by the microprocessor to allow a maximum of different pulse templates. the line length is selected by programming the registers xpm(2:0) as shown for typical values in table 42 below. the transmitter requires an external step up transformer to drive the line. the values are optimized for a transformer ratio of 1:2.4 and cable type pulp 22awg (100 ? ). other external configurations require an adaption of these values. table 41 transmit buffer operating modes (t1/j1) buffer size ts offset programming slip performance bypass enabled no short buffer disabled yes 1 frame enabled yes 2 frames enabled yes table 42 pulse shaper programming (t1/j1) range in m range in ft. xpm0 xpm1 xpm2 xp04- xp00 xp14- xp10 xp24- xp20 xp34- xp30 hexadecimal decimal serial resistor value: 2 ? 0 to 40 0 to 133 95 16 1 40 to 81 133 to 266 b6 1e 1 81 to 122 266 to 399 d9 26 1 122 to 162 399 to 533 fc 36 1 162 to 200 533 to 655 1e c3 1 falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 166 ds1.1, 2003-10-23 hardware description 5.4.6 transmit line monitor (t1/j1) the transmit line monitor compares the transmit line current on xl1 and xl2 with an on-chip transmit line current limiter. the monitor detects faults on the primary side of the transformer indicated by a highly increased transmit line current (more than 120 ma for at least 3 consecutive pulses sourced by v ddx 1) ) and protects the device from damage by setting the transmit line driver xl1/2 into high-impedance state automatically (if enabled by xpm2.daxlt = 0). the current limiter checks the actual current value of xl1/2 and if the transmit line current drops below the detection limit the high-impedance state is cleared. two conditions are detected by the monitor: transmit line de-jitteredity (more than 31 consecutive zeros) indicated by frs1.xlo and transmit line high current indicated by frs1.xls. in both cases a transmit line monitor status change interrupt is provided. serial resistor value: 4 ? 0 to 40 0 to 133 19 9f 1 40 to 81 133 to 266 b6 1e 1 81 to 122 266 to 399 3c 27 1 122 to 162 399 to 533 3e 37 1 162 to 200 533 to 655 5f c3 1 1) shorts between xl1 or xl2 and v ddx are not detected table 42 pulse shaper programming (t1/j1) (cont?d) range in m range in ft. xpm0 xpm1 xpm2 xp04- xp00 xp14- xp10 xp24- xp20 xp34- xp30 hexadecimal decimal falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 167 ds1.1, 2003-10-23 hardware description figure 57 transmit line monitor configuration (t1/j1) 5.4.7 transmit signaling controller (t1/j1) similar to the receive signaling controller the same signaling methods and the same time slot assignment are provided. the falc ? 56 performs the following signaling and data link methods. 5.4.7.1 hdlc or lapd access the transmit signaling controller of the falc ? 56 performs the flag generation, crc generation, zero bit stuffing and programmable idle code generation. buffering of transmit data is done in the 64 byte deep xfifo. the signaling information is internally multiplexed with the data applied to port xdi or xsig. in signaling controller transparent mode, fully transparent data transmission without hdlc framing is performed. optionally the falc ? 56 supports the continuous transmission of the xfifo contents. operating in hdlc or bom mode ?flags? or ?idle? are transmitted as interframe timefill. the falc ? 56 offers the flexibility to insert data during certain time slots. any combinations of time slots can be programmed separately for the receive and transmit direction if using hdlc channel 1. hdlc channel 2 and 3 support one programmable time slot common for receive and transmit direction each. 5.4.7.2 support of signaling system #7 the hdlc controller of channel 1 supports the signaling system #7 (ss7) which is described in itu-q.703. the following description assumes, that the reader is familiar with the ss7 protocol definition. its10936 pulse shaper monitor line tri xdata xl1 xl2 falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 168 ds1.1, 2003-10-23 hardware description ss7 support must be activated by setting the mode register. data stored in the transmit fifo (xfifo) is sent automatically. the ss7 protocol is supported by the following hardware features in transmit direction: transmission of flags at the beginning of each signaling unit bit stuffing (zero insertion) calculation of the crc16 checksum: the transmitter adds the checksum to each signaling unit. each signaling unit written to the transmit fifo (xfifo, 2 32 bytes) is sent once or repeatedly including flags, crc checksum and stuffed bits. after e.g. an msu has been transmitted completely, the falc ? 56 optionally starts sending of fisus containing the forward sequence number (fsn) and the backward sequence number (bsn) of the previously transmitted signa ling unit. setting bit ccr5.afx causes fill in signaling units (fisus) to be sent continuously, if no hdlc or signaling unit (su) is to be transmitted from xfifo. during update of xfifo, automatic transmission is interrupted and resumed after update is completed. the internally generated fisus contain fsn and bsn of the last transmitted signaling unit written to xfifo. using cmdr.xrep = 1, the contents of xfifo can be sent continuously. clearing of cmdr.xres/sres stops the automatic repetition of transmission. this function is also available for hdlc frames, so no flag generation, crc byte generation and bit stuffing is necessary. example: after an msu has been sent repetitively and xrep has been cleared, fisus are sent automatically. 5.4.7.3 cas bit-robbing (t1/j1, serial mode) the signaling controller inserts the bit stream either on the transmit line side or if external signaling is enabled on the transmit system side. signaling data is sourced on port xsig, which is selected by register pc(4:1) and fmr5.eibr = 1. in external signaling mode the signaling data is sampled with the working clock of the transmit system interface (sclkx) together with the transmit synchronous pulse (sypx ). data on xsig is latched in the bit positions 5 to 8 per time slot, bits 1 to 4 are ignored. the fs/dl-bit is sampled on port xsig and inserted in the outgoing data stream. the received cas multiframe is inserted frame aligned into the data stream on xdi. data sourced by the internal signaling controller overwrites the external signaling data which must be valid during the last frame of a multiframe. internal multiplexing of data and signaling data can be disabled on a per time slot basis (clear channel capability). this is also valid when using the internal and external signaling mode. falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 169 ds1.1, 2003-10-23 hardware description 5.4.7.4 cas bit-robbing (t1/j1, p access mode) the signaling controller inserts the bit stream either on the transmit line side or if external signaling is enabled on the transmit system side. signaling data is sourced internally from registers xs(12:1). internal multiplexing of data and signaling data can be disabled on a per time slot basis (clear channel capability). this is also valid when using the internal and external signaling mode. 5.4.7.5 data link access in esf/f24 and f72 format (t1/j1) the dl-channel protocol is supported as follows: access is done on a multiframe basis through registers xdl(3:1) or hdlc access or transparent transmission (non hdlc mode) from xfifo (hdlc channel 1 only) the signaling information stored in the xfifo is inserted in the dl-bits of frame 26 to 72 in f72 format or in every other frame in esf format. transmission can be done on a multiframe boundary (ccr1.xmfa = 1). operating in hdlc or bom mode ?flags? or ?idle? are transmitted as interframe timefill. 5.4.7.6 periodical performance report in esf format (t1/j1) according to ansi t1.403 the falc ? 56 can automatically generate the p eriodical p erformance r eport (ppr) and transmit it every second in the data link channel of the extended superframe format (esf/f24 only). automatic sending of this report can be enabled/disabled by the use of bit ccr5.epr. a single report can be initiated manually at any time (by setting cmdr2.xppr = 1). performance information is sampled every second and the report contains data of the last four seconds as shown in the following tables. falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 170 ds1.1, 2003-10-23 hardware description . table 43 structure of periodical performance report (t1/j1) 1) 1) the rightmost bit (bit 1) is transmitted first for all fields except for the two bytes of the fcs that are transmitted leftmost bit (bit 8) first. octet no.87654321time 1 flag = 01111110 2 sapi = 001110 cr 2) 2) reflects state of bit ccr5.cr ea=0 3 tei = 0000000 ea=1 4 control = 00000011 = unacklowledged frame 5 g3lv g4u1u2g5sl g6t 0 6 fe se lb g1 r g2 nm n1 7 g3lv g4u1u2g5sl g6t 0 -1 s 8 fe se lb g1 r g2 nm n1 9 g3lv g4u1u2g5sl g6t 0 -2 s 10 fe se lb g1 r g2 nm n1 11 g3 lv g4 u1 u2 g5 sl g6 t 0 -3 s 12 fe se lb g1 r g2 nm n1 13 fcs 14 fcs 15 flag = 01111110 falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 171 ds1.1, 2003-10-23 hardware description 5.5 system interface in t1/j1 mode the falc ? 56 offers a flexible feature for system designers where for transmit and receive direction different system clocks and system pulses are necessary. the interface to the receive system highway is realized by two data buses, one for the data rdo and one for the signaling data rsig. the receive highway is clocked on pin sclkr, while the interface to the transmit system highway is independently clocked on pin sclkx. the frequency of these working clocks and the data rate of 2.048/4.096/8.192/16.384/1.544/3.088/6.192/12.352 mbit/s for the receive and transmit system interface is programmable by sic1.ssc1/0, sic2.ssc2 and sic1.ssd1, fmr1.ssd0. selectable system clock and data rates and their valid combinations are shown in the table below. table 44 bit functions in periodical performance report 1) 1) according to ansi t1.403 bit value interpretation g1 = 1 number of crc error events = 1 g2 = 1 1 < number of crc error events 5 g3 = 1 5 < number of crc error events 10 g4 = 1 10 < number of crc error events 100 g5 = 1 100 < number of crc error events 319 g6 = 1 number of crc error events 320 se = 1 severely errored framing event 1 (fe shall be 0) fe = 1 frame synchronization bit error event 1 (se shall be 0) lv = 1 line code violation event 1 sl = 1 slip event 1 lb = 1 payload loop-back activated u1 not used (default value = 0) u2 not used (default value = 0) r not used (default value = 0) nmni one-second report modulo 4 counter falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 172 ds1.1, 2003-10-23 hardware description = valid, - = invalid generally the data or marker on the system interface are clocked off or latched on the rising or falling edge (sic3.resr/x) of the sclkr/x clock. some clocking rates allow transmission of time slots in different channel phases. each channel phase which shall be active on ports rdo, xdi, rp(a:d) and xp(a:d) is programmable by bit sic2.sics(2:0), the remaining channel phases are cleared or ignored. the signals on pin sypr in combination with the assigned time slot offset in register rc0 and rc1 define the beginning of a frame on the receive system highway. the signal on pin sypx or xmfs together with the assigned time slot offset in register xc0 and xc1 define the beginning of a frame on the transmit system highway. adjusting the frame begin (time slot 0, bit 0) relative to sypr/x or xmfs is possible in the range of 0 to 125 s. the minimum shift of varying the time slot 0 begin can be programmed between 1 bit and 1/8 bit depending of the system clocking and data rate, e.g. with a clocking/data rate of 2.048 mhz shifting is done bit by bit, while running the falc ? 56 with 16.384 mhz and 2.048 mbit/s data rate it is done by 1/8 bit. a receive frame marker rfm can be activated during any bit position of the entire frame. programming is done with registers rc1/0. the pin function rfm is selected by pc(4:1).rpc(2:0) = 001. the rfm selection disables the internal time slot assigner, no offset programming is performed. the receive frame marker is active high for one 1.544/2.048 mhz cycle or one system clock cycle (see gpc1.srfm) and is clocked off with the rising or falling edge of the clock which is in/output on port sclkr (see sic3.resx/r). table 45 system clocking and data rates (t1/j1) system data rate clock rate 1.544/2.048 mhz clock rate 3.088/4.096 mhz clock rate 6.176/8.192 mhz clock rate 12.352/16.38 4 mhz 1.544/2.048 mbit/s 3.088/4.096 mbit/s - 6.176/8.192 mbit/s - - 12.352/16.384 mbit/s - - - falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 173 ds1.1, 2003-10-23 hardware description figure 58 system interface (t1/j1) f56v2_system_interface receive signaling buffer receive elastic buffer receive backplane receive jitter attenuator transmit signaling buffer transmit elastic buffer transmit backplane transmit jitter attenuator rsigm rsig rmfb rfm dlr freeze rfsp sclkr dco-r rp(a...d) dco-r sypr rdo sclkx xp(a...d) xdi rclk tclk dco-r receive data receive clock transmit data transmit clock plb byp byp xsig sypx xmfs tclk xsigm xmfb dlx xclk xlt 1 0 1 0 los gpi gpi falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 174 ds1.1, 2003-10-23 hardware description 5.5.1 receive system interface (t1/j1) figure 59 receive system interface clocking (t1/j1) itd10949 ~ ~ ~ ~ frame 1 frame 2 frame 3 frame 11 frame 12 frame 1 frame 2 ~ ~ ~ ~ bit 255 bit 0 bit 255 t 4 mbit interface 2 mbit interface programmable via rc0/1 rdo rmfb sypr sypr sclkr 8.192 mhz 1.544 mhz sclkr 2 mbit/s data rate rdo/rsig rdo/rsig (sclkr = 8.192 mhz) 4 mbit/s data rate rfm receive frame marker rsigm time-slot marker rtr1...4 4 mbit/s data rate (sclkr = 8.192 mhz) rdo/rsig bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 (sclkr = 1.544 mhz) rdo bit 192 fdl bit 1 bit 2 bit 3 bit 4 programmable via rc0/1 t dlr dl bit marker 1.544 mbit interface 1.544 mbit/s data rate 4 mbit interface 2 mbit interface (e.g. f12 frame format) sample edge edge trigger ts0 sample edge marks any bit position marks any time-slot 1) only falling trigger edge shown, depending on bit sic3.resr 1) rco/1 falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 175 ds1.1, 2003-10-23 hardware description 5.5.1.1 receive offset programming depending on the selection of the synchronization signals (sypr or rfm), different calculation formulas are used to define the position of the synchronization pulses. these formulas are given below, see figure 60 to figure 63 for explanation. the pulse length of sypr and rfm is always the basic t1/j1 bit width (648 ns) in 1.544-mhz mode or the e1 bit width (488 ns) in 2.048-mhz mode. this chapter describes the system highway operation in 1.544-mhz mode only. if the system highway is operated in 2.048-mhz mode, the description given in chapter 4.5.1.1 on page 109 applies. sypr offset calculation t: time between beginning of sypr pulse and beginning of next frame (time slot 0, bit 0), measured in number of sclkr clock intervals maximum delay: t max =(193 sc/sd)-1 sd: basic data rate; 1.544 mbit/s sc: system clock rate; 1.544, 3.088, 6.176, or 12.352 mhz x: programming value to be written to registers rc0 and rc1 (see page 375 ). 0 t 4: x = 4 - t + (7 sc/sd) 5 t t max : x = (200 sc/sd) + 4 - t rfm offset calculation mp: marker position of rfm, counting in sclkr clock cycles (0 = f-bit) sc = 1.544 mhz: 0 mp 192 sc = 3.088 mhz: 0 mp 385 sc = 6.176 mhz: 0 mp 771 sc = 12.352 mhz: 0 mp 1543 sd: basic data rate; 1.544 mbit/s sc: system clock rate; 1.544, 3.088, 6.176, or 12.352 mhz x: programming value to be written to registers rc0 and rc1 (see page 375 ). 0 mp 193 (sc/sd)-3: x=mp+2+(7 sc/sd) 193 (sc/sd)-2 mp 193 (sc/sd)-1: x=mp+2-(186 sc/sd) falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 176 ds1.1, 2003-10-23 hardware description figure 60 sypr offset programming (1.544 mbit/s, 1.544 mhz) figure 61 sypr offset programming (6.176 mbit/s, 6.176 mhz) f0222a 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 rdo 1 2 3 4 5 6 7 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 ts0 ts1 ts24 ts0 ts1 sypr sclkr sic3.resr = 0 (falling edge) sclkr sic3.resr = 1 (rising edge) t = 0 sypr t t sypr f f f0222b sypr sclkr sic3.resr = 0 (falling edge) sclkr sic3.resr = 1 (rising edge) t = 0 sypr t t sypr bit-interleaved (ts = time slot, cp = channel phase) rdo (cp0) 1 2 3 ts24 ts0 rdo (cp1) rdo (cp2) f f f f rdo (cp3) f 1 1 1 2 2 2 3 3 3 8 8 8 8 7 7 7 f f f 1 2 3 4 1 1 1 2 2 2 3 3 3 ts0 falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 177 ds1.1, 2003-10-23 hardware description figure 62 rfm offset programming (1.544 mbit/s, 1.544 mhz) figure 63 rfm offset programming (6.176 mbit/s, 6.176 mhz) f0222c 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 rdo 1 2 3 4 5 6 7 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 ts0 ts24 ts0 ts1 rfm sclkr sic3.resr = 0 (falling edge) sclkr sic3.resr = 1 (rising edge) bp = 0 rfm rfm bp = 12 bp = 188 f f (bp = bit position) f0222d rdo (cp0) sclkr sic3.resr = 0 (falling edge) sclkr sic3.resr = 1 (rising edge) bit-interleaved (ts = time slot, cp = channel phase, bp = bit position) 1 2 3 ts24 rfm bp = 0 rfm rfm bp = 12 bp = 1020 ts0 rdo (cp1) rdo (cp2) f f f f rdo (cp3) f 1 1 1 2 2 2 3 3 3 8 8 8 8 7 7 7 f f f 1 2 3 4 1 1 1 2 2 2 3 3 3 ts0 falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 178 ds1.1, 2003-10-23 hardware description figure 64 2.048 mhz receive signaling highway (t1/j1) figure 65 receive fs/dl-bits in time slot 0 on rdo (t1/j1) f0135 a b c d 4 5 6 7 0 1 2 3 4 5 6 7 ts31 ts0 ts1 rsig rdo sclkr sypr t 125 s t = time slot offset (rc0, rc1) f = fs/dl-bit abcd = signaling bits for time slots 1...24, time slot mapping according to channel translation mode 0 f a b c d 0 1 2 3 4 5 6 7 ts2 a b c d 0 1 2 3 4 5 6 7 ts3 a b c d ts4 a b c d fs/dl- channel idle-channel 0 1 2 3 itd06460 12345678 fs/dl time-slot msb lsb fs/dl data bit fs/dl falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 179 ds1.1, 2003-10-23 hardware description figure 66 1.544 mhz receive signaling highway (t1/j1) 5.5.2 transmit system interface (t1/j1) compared to the receive paths the inverse functions are performed for the transmit direction. the interface to the transmit system highway is realized by two data buses, one for the data xdi and one for the signaling data xsig. the time slot assignment is equivalent to the receive direction. all unequipped (idle) time slots are ignored. latching of data is controlled by the system clock (sclkx or sclkr) and the synchronization pulse (sypx /xmfs) in combination with the programmed offset values for the transmit time slot/clock slot counters xc1/0. the frequency of the working clock 2.048/4.096/8.192/16.384 mhz or 1.544/3.088/6.176/12.352 mhz for the transmit system interface is programmable by sic1.ssc1/0 and sic2.ssc2. refer also table 45 . the received bit stream on ports xdi and xsig can be multiplexed internally on a time slot basis, if enabled by sic3.ttrf = 1. the data received on port xsig can be sampled if the transmit signaling marker xsigm is active high. data on port xdi is sampled if xsigm is low for the corresponding time slot. programming the xsigm marker is done with registers ttr(4:1). note: xsig is required in the last frame of a multiframe only and ignored in all other frames. f0134 a b c d 4 5 6 7 0 1 2 3 4 5 6 7 ts23 ts0 ts1 a b c d 0 1 2 3 4 5 6 7 ts23 rsig rdo sclkr sypr t 125 s t = time slot offset (rc0, rc1) f= fs/dl-bit abcd, abab = signaling bits for time slots 1...23 0 1 2 3 4 5 6 7 a b c d a b c d f f f f esf f12 a b a b a b a b rsig a b a b a b a b f f falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 180 ds1.1, 2003-10-23 hardware description figure 67 transmit system clocking: 1.544 mhz (t1/j1) frame1 frame2 frame3 frame12 frame1 frame2 frame3 xdi xmfb xmfs sypx trigger edge 1) bit 0 sample edge 1) sclkx xdi fdl bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 dlx dl bit marker 1) only falling edge mode shown 2) delay t is programmable by xc0/1; sypx t 2) xsigm time slot marker f0005 falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 181 ds1.1, 2003-10-23 hardware description figure 68 transmit system clocking: 8.192 mhz/4.096 mbit/s (t1/j1) frame1 frame2 frame3 frame12 frame1 frame2 frame3 xdi xmfs sypx trigger edge 1) bit 0 sample edge 1) sclkx xdi/xsig sic2.sics2-0=000 dlx dl-bit marker sic2.sics2-0=000 1) only falling e dge mode shown 2) delay t is programmable by xc0/1; sypx t 2) 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 dlx dl-bit marker sic2.sics2-0=001 xdi/xsig sic2.sics2-0=001 xsigm time-slot marker xtr1...4 sic2.sics2-0=000(001) f0006 falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 182 ds1.1, 2003-10-23 hardware description figure 69 2.048 mhz transmit signaling clocking (t1/j1) figure 70 1.544 mhz transmit signaling highway (t1/j1) f0136 a b c d 4 5 6 7 0 1 2 3 4 5 6 7 ts31 ts0 ts1 xsig xdi sclkx sypx t 125 s t = time slot offset (rc0, rc1) f = fs/dl-bit abcd = signaling bits for time slots 1...24, time slot mapping according to channel translation mode 0, read only during last frame of a multiframe f a b c d 0 1 2 3 4 5 6 7 ts2 a b c d 0 1 2 3 4 5 6 7 ts3 a b c d ts4 a b c d fs/dl- channel idle-channel 0 1 2 3 f0137 a b c d 4 5 6 7 0 1 2 3 4 5 6 7 ts23 ts0 ts1 a b c d 0 1 2 3 4 5 6 7 ts23 xsig xdi sclkx sypx t 125 s t = time slot offset (rc0, rc1) f= fs/dl-bit abcd = esf signaling bits for time slots 1...23 read only during last frame of a multiframe, abab = f12 signaling bits for time slots 1...23 read only during last frame of a multiframe (bit positions 4/5) 0 1 2 3 4 5 6 7 a b c d a b c d f f f f esf f12 a b a b a b a b xsig a b a b a b a b f f falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 183 ds1.1, 2003-10-23 hardware description figure 71 signaling marker for cas/cas-cc applications (t1/j1) f56v2_cas_marker_1 rdo xdi rmfb xmfb rdo xdi rsigm 1) xsigm rdo xdi rsigm 1) xsigm fs/ dl 1 2 3 4 5 6 7 8 9 19 20 21 22 23 24 fs/ dl 1 24 fs/ dl 1 2 3 4 5 6 19 20 21 22 23 24 fs/ dl 1 notes: 1) rsigm and xsigm are programmed to mark only channel 24 in this example (via rtr(4:1) and ttr(4:1)). a: channel translation mode 0 b: channel translation mode 1 frame 1 frame 6 frame 12 frame 1 multiframe n (f12 for example) falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 184 ds1.1, 2003-10-23 hardware description figure 72 signaling marker for cas-br applications (t1/j1) f56v2_cas_marker_2 rdo xdi frame 1 frame 6 frame 12 frame 1 rmfb xmfb rdo xdi rsigm 1) xsigm rdo xdi rsigm 1) xsigm fs/ dl 1 2 3 4 5 6 7 8 9 19 20 21 22 23 24 fs/ dl 1 24 fs/ dl 1 2 3 4 5 6 19 20 21 22 23 24 fs/ dl 1 notes: 1) rsigm and xsigm mark the robbed bit positions in frames 6 and 12 of each multiframe, if xco.brm is set high. 2) robbed-bit marker every second frame 2) a: channel translation mode 0 b: channel translation mode 1 multiframe n (f12 for example) falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 185 ds1.1, 2003-10-23 hardware description fs/dl data on system transmit highway (xdi), time slot 0: figure 73 transmit fs/dl bits on xdi (t1/j1) 5.5.2.1 transmit offset programming the pulse length of sypr and rfm is always the basic t1/j1 bit width (648 ns) in 1.544-mhz mode or the e1 bit width (488 ns) in 2.048-mhz mode. this chapter describes the system highway operation in 1.544-mhz mode only. if the system highway is operated in 2.048-mhz mode, the description given in chapter 4.5.2.1 on page 114 applies. sypx offset calculation t: time between the active edge of sclkx after sypx pulse begin and beginning of the next frame (f-bit, channel phase 0), measured in number of sclkx clock intervals; maximum delay: t max =(200 sc/bf)-(7 sc/bf)-1 bf: basic frequency; 1.544 mbit/s sc: system clock rate; 1.544, 3.088, 6.176, or 12.352 mhz x: programming value to be written to registers rc0 and rc1 (see page 372 ). 0 t 4: x = 3 - t + (7 sc/bf) 5 t t max : x = (200 sc/bf)-t+3 itd06460 12345678 fs/dl time-slot msb lsb fs/dl data bit fs/dl falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 186 ds1.1, 2003-10-23 hardware description figure 74 sypx offset programming (1.544 mbit/s, 1.544 mhz) figure 75 sypx offset programming (6.176 mbit/s, 6.176 mhz) f0224a 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 xdi 1 2 3 4 5 6 7 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 ts1 ts2 ts24 ts1 ts2 sypx sclkx sic3.resx = 1 (rising edge) sclkx sic3.resx = 0 (falling edge) t = 0 sypx t t sypx f f f0224b sypx sclkx sic3.resx = 1 (rising edge) sclkx sic3.resx = 0 (falling edge) t = 0 sypx t t sypx bit-interleaved (ts = time slot) xdi (cp0) 1 2 3 ts24 ts1 xdi (cp1) xdi (cp2) f f f f xdi (cp3) f 1 1 1 2 2 2 3 3 3 8 8 8 8 7 7 7 f f f 1 2 3 4 1 1 1 2 2 2 3 3 3 ts1 falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 187 ds1.1, 2003-10-23 hardware description 5.5.3 time slot assigner (t1/j1) hdlc channel 1 offers the flexibility to connect data during certain time slots, as defined by registers rtr(4:1) and ttr(4:1), to the rfifo and xfifo, respectively. any combinations of time slots can be programmed for the receive and transmit directions. if ccr1.eits = 1 the selected time slots (rtr(4:1)) are stored in the rfifo of the signaling controller and the xfifo contents is inserted into the transmit path as controlled by registers ttr(4:1). for hdlc channels 2 and 3, one out of 24 time slots can be selected for each channel, but in common for transmit and receive direction. within selected time slots single bit positions can be masked to be used/not used for hdlc transmission for all hdlc channels. additionally, the use of even, odd or both frames can be selected for each hdlc channel individually. table 46 time slot assigner hdlc channel 1 (t1/j1) receive time slot register transmit time slot register time slot receive time slot register transmit time slot register time slot rtr 1.7 ttr 1.7 0 rtr 3.7 ttr 3.7 16 rtr 1.6 ttr 1.6 1 rtr 3.6 ttr 3.6 17 rtr 1.5 ttr 1.5 2 rtr 3.5 ttr 3.5 18 rtr 1.4 ttr 1.4 3 rtr 3.4 ttr 3.4 19 rtr 1.3 ttr 1.3 4 rtr 3.3 ttr 3.3 20 rtr 1.2 ttr 1.2 5 rtr 3.2 ttr 3.2 21 rtr 1.1 ttr 1.1 6 rtr 3.1 ttr 3.1 22 rtr 1.0 ttr 1.0 7 rtr 3.0 ttr 3.0 23 rtr 2.7 ttr 2.7 8 rtr 4.7 ttr 4.7 24 rtr 2.6 ttr 2.6 9 rtr 4.6 ttr 4.6 25 rtr 2.5 ttr 2.5 10 rtr 4.5 ttr 4.5 26 rtr 2.4 ttr 2.4 11 rtr 4.4 ttr 4.4 27 rtr 2.3 ttr 2.3 12 rtr 4.3 ttr 4.3 28 rtr 2.2 ttr 2.2 13 rtr 4.2 ttr 4.2 29 rtr 2.1 ttr 2.1 14 rtr 4.1 ttr 4.1 30 rtr 2.0 ttr 2.0 15 rtr 4.0 ttr 4.0 31 falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 188 ds1.1, 2003-10-23 hardware description the format for receive fs/dl data transmission in time slot 0 of the system interface is as shown in figure 67 below. in order to get an undisturbed reception even in the asynchronous state bit fmr2.dais has to be set. 5.6 test functions (t1/j1) 5.6.1 pseudo-random binary sequence generation and monitor the falc ? 56 has the added ability to generate and monitor a 2 15 -1 and 2 20 -1 pseudo- random binary sequences (prbs). the generated prbs pattern is transmitted to the remote end on pins xl1/2 or xdop/n and can be inverted optionally. generating and monitoring of prbs pattern is done according to itu-t o.151 and tr62411 with maximum 14 consecutive zero restriction. the prbs monitor senses the prbs pattern in the incoming data stream. synchronization is done on the inverted and non-inverted prbs pattern. the current synchronization status is reported in status and interrupt status registers. enabled by bit lcr1.eprm each prbs bit error increments an error counter (bec). synchronization is reached within 400 ms with a probability of 99.9% and a bit error rate of up to 10 -1 . the prbs generator and monitor can be used to handle either a framed (tpc0.fra = 1) or an unframed (tpc0.fra = 0) data stream. 5.6.2 remote loop in the remote loop-back mode the clock and data recovered from the line inputs rl1/2 or rdip/rdin are routed back to the line outputs xl1/2 or xdop/xdon through the analog or digital transmitter. as in normal mode they are also processed by the synchronizer and then sent to the system interface.the remote loop-back mode is selected by setting the corresponding control bits lim1.rl+jatt. received data is looped with or without use of the transmit jitter attenuator (fifo). falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 189 ds1.1, 2003-10-23 hardware description figure 76 remote loop (t1/j1) its09750 rdo xdi rclk rl1 rl2 xl1 xl2 fifo xclk rclk dco-r/x framer rec. framer trans. store elast. elast. store recovery data clock + mux mux falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 190 ds1.1, 2003-10-23 hardware description 5.6.3 payload loop-back to perform an effective circuit test a line loop is implemented. if the payload loop-back (fmr2.plb) is activated the received 192 bits of payload data is looped back to the transmit direction. the framing bits, crc6 and dl-bits are not looped, if fmr4.tm = 0. they are originated by the falc ? 56 transmitter. if fmr4.tm = 1 the received fs/dl-bit is sent transparently back to the line interface. following pins are ignored: xdi, xsig, tclk, sclkx, sypx and xmfs. all the received data is processed normally. with bit fmr2.sais an ais can be sent to the system interface on pin rdo. figure 77 payload loop (t1/j1) its09748 clock + data rec. framer elast. store trans. framer rdo xdi rclk rl1 rl2 xl1 xl2 recovery sclkx sclkr mux ais-gen elast. store falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 191 ds1.1, 2003-10-23 hardware description 5.6.4 local loop the local loop-back mode, selected by lim0.ll = 1, disconnects the receive lines rl1/2 or rdip/rdin from the receiver. instead of the signals coming from the line the data provided by system interface are routed through the analog receiver back to the system interface. however, the bit stream is transmitted undisturbedly on the line. an ais to the distant end can be enabled by setting fmr1.xais without influencing the data looped back to the system interface. note that enabling the local loop usually invokes an out of frame error until the receiver resynchronizes to the new framing. the serial codes for transmitter and receiver have to be identical. figure 78 local loop (t1/j1) its09749 rdo xdi rclk ais-gen rl1 rl2 xl1 xl2 framer rec. framer trans. store elast. recovery data clock + mux elast. store falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 192 ds1.1, 2003-10-23 hardware description 5.6.5 single channel loop-back (loop-back of time slots) the channel loop-back is selected by loop.eclb = 1. each of the 24 time slots can be selected for loop-back from the system pcm input (xdi) to the system pcm output (rdo). this loop-back is programmed for one time slot at a time selected by register loop. during loop-back, an idle channel code programmed in register idle is transmitted to the remote end in the corresponding pcm route time slot. for the time slot test, sending sequences of test patterns like a 1-khz check signal should be avoided. otherwise an increased occurrence of slips in the tested time slot disturbs testing. these slips do not influence the other time slots and the function of the receive memory. the usage of a quasi-static test pattern is recommended. figure 79 channel loop-back (t1/j1) its09747 rdo xdi rclk rl1 rl2 xl1 xl2 idle code framer trans. framer rec. store elast. store elast. mux mux recovery data clock + falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 193 ds1.1, 2003-10-23 hardware description 5.6.6 alarm simulation (t1/j1) alarm simulation does not affect the normal operation of the device, i.e. all time slots remain available for transmission. however, possible real alarm conditions are not reported to the processor or to the remote end when the device is in the alarm simulation mode. the alarm simulation is initiated by setting the bit fmr0.sim. the following alarms are simulated: loss-of-signal (los, red alarm) alarm indication signal (ais, blue alarm) loss of pulse frame remote alarm (yellow alarm) indication receive and transmit slip indication framing error counter code violation counter crc6 error counter some of the above indications are only simulated if the falc ? 56 is configured in a mode where the alarm is applicable. the alarm simulation is controlled by the value of the alarm simulation counter: frs2.esc which is incremented by setting bit fmr0.sim. clearing of alarm indications: automatically for los, remote (yellow) alarm, ais, and loss of synchronization and user controlled for slips by reading the corresponding interrupt status register isr3. error counter have to be cleared by reading the corresponding counter registers. is only possible at defined counter steps of frs2.esc. for complete simulation (frs2.esc = 0), eight simulation steps are necessary. 5.6.7 single bit defect insertion single bit defects can be inserted into the transmit data stream for the following functions: fas defect, multiframe defect, crc defect, cas defect, prbs defect and bipolar violation. defect insertion is controlled by register ierr. 5.7 j1-feature overview the japanese j1 standard is very similar to the t1 standard, but differs in some details. to support these differences easily, the following features are provided within the falc ? 56: falc ? 56 pef 2256 h/e functional description t1/j1 user?s manual 194 ds1.1, 2003-10-23 hardware description crc6 generation and checking according to itu-jt g.706 (crc checksum calculation includes fs/dl-bits, see chapter 5.2.6.3 on page 150 ) remote alarm handling according to itu-jt g.704 (remote alarm pattern in dl-channel is "1111111111111111", see chapter 5.2.6.2 on page 150 ) ntt synchronization requirements in esf framing mode pulse shaping according to jt g.704 receive input thresholds according to itu-jt g.703 j1 mode is globally selected by setting rc0.sjr = 1 (see page 373 ). for specific j1 framer initialization see table 57 on page 208 . no special pulse mask setting is required, the described t1-settings also fulfill the j1 requirements. falc ? 56 pef 2256 h/e operational description e1 user?s manual 195 ds1.1, 2003-10-23 hardware description 6 operational description e1 6.1 operational overview e1 the falc ? 56 can be operated in two modes, which are either e1 mode or t1/j1 mode. the device is programmable via a microprocessor interface which enables byte or word access to all control and status registers. after reset the falc ? 56 must be initialized first. general guidelines for initialization are described in chapter 6.3 . the status registers are read-only and are updated continuously. normally, the processor reads the status registers periodically to analyze the alarm status and signaling data. 6.2 device reset e1 the falc ? 56 is forced to the reset state if a low signal is input on pin res for a minimum period of 10 s. during reset the falc ? 56 needs an active clock on pin mclk. all output stages are in a high-impedance state, all internal flip-flops are reset and most of the control registers are initialized with default values. signals (for example rl1/2 receive line) should not be applied before the device is powered up. after reset the device is initialized to e1 operation. 6.3 device initialization in e1 mode after reset, the falc ? 56 is initialized for doubleframe format with register values listed in the following table. table 47 initial values after reset (e1) register reset value meaning gcm(8:1) all 00 h 2.048 mhz on pin mclk. fmr0 00 h nrz coding, no alarm simulation. fmr1 fmr2 00 h e1-doubleframe format, 2 mbit/s system data rate, no ais transmission to remote end or system interface, payload loop off. sic1 sic2, sic3 00 h 00 h 00 h 8.192 mhz system clocking rate, receive buffer 2 frames, transmit buffer bypass, data sampled or transmitted on the falling edge of sclkr/x, automatic freeze signaling, data is active in the first channel phase falc ? 56 pef 2256 h/e operational description e1 user?s manual 196 ds1.1, 2003-10-23 hardware description loop xsw xsp tswm 00 h 00 h 00 h 00 h channel loop-back and single frame mode are disabled. all bits of the transmitted service word are cleared. spare bit values are cleared. no transparent mode active. xc0 xc1 00 h 9c h the transmit clock offset is cleared. the transmit time slot offset is cleared. rc0 rc1 00 h 9c h the receive clock slot offset is cleared. the receive time slot offset is cleared. idle icb(4:1) 00 h 00 h idle channel code is cleared. normal operation (no ?idle channel? selected). lim0 lim1 pcd pcr 00 h 00 h 00 h 00 h slave mode, local loop off analog interface selected, remote loop off pulse count for los detection cleared pulse count for los recovery cleared xpm(2:0) 40 h, 03 h , 7b h transmit pulse mask (transmitter in tristate mode) imr(5:0) ff h all interrupts are disabled rtr(4:1) ttr(4:1) tss2 tss3 all 00 h all 00 h 00 h 00 h no time slots selected gcr 00 h internal second timer, power on cmr1 00 h rclk output: dpll clock, dco-x enabled, dco-x internal reference clock cmr2 00 h sclkr selected, sclkx selected, receive synchronization pulse sourced by sypr , transmit synchronization pulse sourced by sypx mode mode2 mode3 00 h 00 h 00 h signaling controller disabled rah(2:1) ral(2:1) fd h , ff h ff h , ff h compare register for receive address cleared table 47 initial values after reset (e1) (cont?d) register reset value meaning falc ? 56 pef 2256 h/e operational description e1 user?s manual 197 ds1.1, 2003-10-23 hardware description e1 initialization for a correct start up of the primary access interface a set of parameters specific to the system and hardware environment must be programmed after reset goes inactive. both the basic and the operational parameters must be programmed before the activation procedure of the pcm line starts. such procedures are specified in itu-t and etsi recommendations (e.g. fault conditions and consequent actions). setting optional parameters primarily makes sense when basi c operation via the pcm line is guaranteed. table 48 gives an overview of the most important parameters in terms of signals and control bits which are to be programmed in one of the above steps. the sequence is recommended but not mandatory. accordingly, parameters for the basic and operational set up, for example, can be programmed simultaneously. the bit fmr1.pmod should always be kept low (otherwise t1/j1 mode is selected). pc(4:1) 00 h, 00 h 00 h, 00 h input function of ports rp(a to d): sypr , input function of ports xp(a to d): sypx pc5 pc6 00 h 00 h sclkr, sclkx, rclk configured to inputs, xmfs active low, clk1 and clk2 pin configuration the activity level of port xmfs can be selected to be active high or active low by programming pc5.cxmfs. this bit must not be set, if xmfs is not enabled as an input. xmfs input selection is done by programming one of the transmit multifunction ports, using registers pc4(4:1).xpc(3:0). note: xmfs must not be used together with sypx on different multifunction ports. table 48 initialization parameters (e1) configuration register setting basic set up master clocking mode gcm(8:1) according to external mclk clock frequency e1 mode select fmr1.pmod = 0 specification of line interface and clock generation lim0, lim1, xpm(2:0) line interface coding fmr0.xc(1:0), fmr0.rc(1:0) loss-of-signal detection/recovery conditions pcd, pcr, lim1, lim2 table 47 initial values after reset (e1) (cont?d) register reset value meaning falc ? 56 pef 2256 h/e operational description e1 user?s manual 198 ds1.1, 2003-10-23 hardware description features like channel loop-back, idle channel activation, extensions for signaling support, alarm simulation, etc. are activated later. transmission of alarms (e.g. ais, remote alarm) and control of synchronization in connection with consequent actions to remote end and internal system depend on the activation procedure selected. note: read access to unused register addresses: value should be ignored. write access to unused register addresses: should be avoided, or set to 00 h in address range up to af h ; must be avoided in address range above af h if not defined elsewhere. all control registers (except xfifo, xs(16:1), cmdr, dec) are of type read/ write. system clocking and data rate sic1.sscc(1:0), sic1.ssd1,fmr1.ssd0 cmr2.irsp/irsc/ixsp/ixsc transmit offset counters xc0.xco, xc1.xto receive offset counters rc0.rco, rc1.rto ais to system interface fmr2.dais/sais operational set up select framing fmr2.rfs(1:0), fmr1.xfs framing additions rc1.asy4, rc1.swd synchronization mode fmr1.afr, fmr2.almf signaling mode xsp, xsw, fmr1.ensa, xsa(8:4), tswm, mode, ccr1, ccr2, rah(2:1), ral(2:1) table 48 initialization parameters (e1) (cont?d) configuration register setting falc ? 56 pef 2256 h/e operational description e1 user?s manual 199 ds1.1, 2003-10-23 hardware description specific e1 register settings the following is a suggestion for a basic initialization to meet most of the e1 requirements. depending on different applications and requirement any other initialization can be used. e1 framer initialization the selection of the following modes during the basic initialization supports the etsi requirements for e-bit access, remote alarm and synchronization (please refer also to falc ? 56 driver code of the evaluation system easy22554 and application notes) and helps to reduce the software load. they are very helpful especially to meet requirements as specified in ets300 011. table 49 line interface initialization (e1) register setting function fmr0.xc0/ fmr0.rc0/ lim1.drs fmr3.cmi the falc ? 56 supports requirements for the analog line interface as well as the digital line interface. for the analog line interface the codes ami and hdb3 are supported. for the digital line interface modes (dual- or single-rail) the falc ? 56 supports ami, hdb3, cmi (with and without hdb3 precoding) and nrz. pcd = 0a h los detection after 176 consecutive ?zeros? (fulfills g.775). pcr = 15 h los recovery after 22 ?ones? in the pcd interval (fulfills g.775). lim1.ril(2:0) = 02 h los threshold of 0.6 v (fulfills g.775). table 50 framer initialization (e1) register setting function xsp.axs = 1 ets300 011 c4.x for instance requires the sending of e-bits in ts0 if crc4 errors have been detected. by programming xsp.axs = 1 the submultiframe status is inserted automatically in the next outgoing multiframe. xsp.ebp = 1 if the falc ? 56 has reached asynchronous state the e-bit is cleared if xsp.ebp = 0 and set if xsp.ebp = 1. ets 300 011 requires that the e-bit is set in asynchronous state. fmr2.axra = 1 the transmission of rai via the line interface is done automatically by the falc ? 56 in case of loss of frame alignment (frs0.lfa = 1). if basic framing has been reinstalled rai is automatically reset. falc ? 56 pef 2256 h/e operational description e1 user?s manual 200 ds1.1, 2003-10-23 hardware description fmr2.frs(2:1) = 10 fmr1.afr = 1 in this mode a search of double framing is automatically restarted, if no crc4 multiframing is found within 8ms. together with fmr2.axra = 1 this mode is essential to meet ets300 011 and reduces the processor load heavily. fmr2.almf = 1 the receiver initiates a new basic- and multiframing research if more than 914 crc4 errors have been detected in one second. fmr2.frs1/0 = 11 in the interworking mode the falc ? 56 stays in double framing format if no multiframe pattern is found in a time interval of 400 ms. this is also indicated by a 400 ms interrupt. additionally the extended interworking mode (fmr3.extiw = 1) will activate after 400 ms the remote alarm (fmr2.axra = 1) and will still search the multiframing without switching completely to the double framing. a complete resynchronization in an 8 ms interval is not initiated. table 51 hdlc controller initialization (e1) register setting function mode = 88 h mode2= 88 h mode3= 88 h hdlc channel 1, 2, and 3receivers active on line side, no address comparison. ccr1 = 18 h ccr3= 08 h ccr4= 08 h enable signaling via ts(31:0), interframe time fill with continuous flags (channel 1). interframe time fill with continuous flags (channel 2). interframe time fill with continuous flags (channel 3). table 50 framer initialization (e1) (cont?d) register setting function falc ? 56 pef 2256 h/e operational description e1 user?s manual 201 ds1.1, 2003-10-23 hardware description note: after the device initialization a software reset should be executed by setting of bits cmdr.xres/rres. 6.4 digital clock interface mode the falc ? 56 can be used to receive and transmit clock information instead of data according to itu-t g.703, chapter 13. the configuration for this mode is 2.048 mhz input clock on rl1/rl2 2.048 mhz output clock on xl1/xl2 transmit clock referenced by sclkx (cmr1.dxss = 0) transmit pulse mask set to xmp0 = ff h , xpm1 = bd h , and xpm2 = 07 h imr0.rme = 0 imr0.rpf = 0 imr1.xpr = 0 imr4.rme2=0 imr4.rpf2=0 imr5.xpr2=0 imr5.rme3=0 imr5.rpf3=0 imr5.xpr3=0 unmask interrupts for hdlc processor requests. rtr3.ts16 = 1 ttr3.ts16 = 1 tseo = 00 h tsbs1 = ff h tsbs2= ff h tsbs3= ff h tss2= 01 h tss3= 02 h select ts16 for hdlc data reception and transmission. even and odd frames are used for hdlc reception and transmission. select all bits of selected time slot (channel 1). select all bits of selected time slot (channel 2). select all bits of selected time slot (channel 3). select time slot 1 for hdlc channel 2. select time slot 2 for hdlc channel 3. table 52 cas-cc initialization (e1) register setting function xsp.casen = 1 ccr1.eits = 0 send cas info stored in the xs(16:1) registers. imr0.casc = 0 enable interrupt with any data change in the rs(16:1) registers. table 51 hdlc controller initialization (e1) (cont?d) register setting function falc ? 56 pef 2256 h/e operational description e1 user?s manual 202 ds1.1, 2003-10-23 hardware description 6.5 output signal tristate modes some output signals can be switched into tristate mode if unused or for wired-or configurations. see table 53 for more detail. table 53 output tristate programming (e1) signal tristate mode selection note rclk pc5.crp = 0 internal pull-up active rdo rsig sic3.rtri = 1 during inactive channel phases only sec/fsc sic3.fsct = 1 b rpa pc1.rpc(3:0) = 1001 b internal pull-up active rpb pc2.rpc(3:0) = 1001 b internal pull-up active rpc pc3.rpc(3:0) = 1001 b internal pull-up active rpd pc4.rpc(3:0) = 1001 b internal pull-up active xpa pc1.xpc(3:0) = 1001 b internal pull-up active xpb pc2.xpc(3:0) = 1001 b internal pull-up active xpc pc3.xpc(3:0) = 1001 b internal pull-up active xpd pc4.xpc(3:0) = 1001 b internal pull-up active xl1 xl2 xpm2.xlt = 1 b or pc1.xpc(3:0) = 1000 b and xpa = high or pc2.xpc(3:0) = 1000 b and xpb = high or pc3.xpc(3:0) = 1000 b and xpc = high or pc4.xpc(3:0) = 1000 b and xpd = high d(15:0) wr =low falc ? 56 pef 2256 h/e operational description t1/j1 user?s manual 203 ds1.1, 2003-10-23 hardware description 7 operational description t1/j1 7.1 operational overview t1/j1 the falc ? 56 can be operated in two principle modes, which are either e1 mode or t1/ j1 mode. the device is programmable via a microprocessor interface which enables byte or word access to all control and status registers. after reset the falc ? 56 must be initialized first. general guidelines for initialization are described in chapter 7.3 the status registers are read-only and are updated continuously. normally, the processor reads the status registers periodically to analyze the alarm status and signaling data. 7.2 device reset t1/j1 the falc ? 56 is forced to the reset state if a low signal is input on pin res for a minimum period of 10 s. during reset the falc ? 56 needs an active clock on pin mclk. all output stages are in a high-impedance state, all internal flip-flops are reset and most of the control registers are initialized with default values. signals (for example rl1/2 receive line) should not be applied before the device is powered up. after reset the device is initialized to e1 operation. 7.3 device initialization in t1/j1 mode after reset, the falc ? 56 is initialized for e1 doubleframe format. to initialize t1/j1 mode, bit fmr1.pmod has to be set high. after the internal clocking is settled to t1/ j1mode (takes up to 20 s), the following register values are initialized: . table 54 initial values after reset and fmr1.pmod = 1 (t1/j1) register initiated value meaning gcm(8:1) all 00 h 1.544 mhz on pin mclk. fmr0 00 h nrz coding, no alarm simulation fmr1 fmr2 00 h 00 h pcm24 mode, 2.048 mbit/s system data rate, no ais transmission to remote end or system interface, payload loop off, channel translation mode 0 falc ? 56 pef 2256 h/e operational description t1/j1 user?s manual 204 ds1.1, 2003-10-23 hardware description sic1 sic2, sic3 00 h 00 h 00 h 2.048 mhz system clocking rate, receive buffer 2 frames, transmit buffer bypass, data sampled or transmitted on the falling edge of sclkr/x, automatic freeze signaling, data is active in the first channel phase loop 00 h loop-backs are disabled. fmr4 fmr5 00 h 00 h remote alarm indication towards remote end is disabled. lfa condition: 2 out of 4/5/6 framing bits, non-auto- synchronization mode, f12 multiframing, internal bit robbing access disabled xc0 xc1 00 h 9c h the transmit clock slot offset is cleared. the transmit time slot offset is cleared. rc0 rc1 00 h 9c h the receive clock slot offset is cleared. the receive time slot offset is cleared. idle icb(3:1) 00 h 00 h idle channel code is cleared. normal operation (no ?idle channels? selected). ccb(3:1) 00 h normal operation (no clear channel operation). lim0 lim1 pcd pcr 00 h 00 h 00 h 00 h slave mode, local loop off, analog interface selected, remote loop off pulse count for los detection cleared pulse count for los recovery cleared xpm(2:0) 40 h ,03 h ,7b h transmit pulse mask (transmitter in tristate mode) imr(5:0) ff h all interrupts are disabled gcr 00 h internal second timer, power on cmr1 00 h rclk output: dpll clock, dco-x enabled, dco-x internal reference clock cmr2 00 h sclkr selected, sclkx selected, receive synchronization pulse sourced by sypr , transmit synchronization pulse sourced by sypx gpc1 00 h sec port input active high pc(4:1) 00 h, 00 h 00 h, 00 h input function of ports rp(a to d): sypr , input function of ports xp(a to d): sypx table 54 initial values after reset and fmr1.pmod = 1 (t1/j1) (cont?d) register initiated value meaning falc ? 56 pef 2256 h/e operational description t1/j1 user?s manual 205 ds1.1, 2003-10-23 hardware description t1/j1 initialization for a correct start up of the primary access interface a set of parameters specific to the system and hardware environment must be programmed after res goes inactive (high). both the basic and the operational parameters must be programmed before the activation procedure of the pcm line starts. such procedures are specified in itu-t recommendations (e.g. fault conditions and consequent actions). setting optional parameters primarily makes sense when basi c operation via the pcm line is guaranteed. table 55 gives an overview of the most important parameters in terms of signals and control bits which are to be programmed in one of the above steps. the sequence is recommended but not mandatory. accordingly, parameters for the basic and operational set up, for example, can be programmed simultaneously. the bit fmr1.pmod must always be kept high (otherwise e1 mode is selected). j1 mode is selected by additionally setting rc0.sjr = 1. features like channel loop-back, idle channel activation, clear channel activation, extensions for signaling support, alarm simulation, etc. are activated later. transmission of alarms (e.g. ais, remote alarm) and control of synchronization in connection with pc5 pc6 00 h 00 h sclkr, sclkx, rclk configured to inputs, xmfs active low, clk1 and clk2 pin configuration the activity level of port xmfs can be selected to be active high or active low by programming pc5.cxmfs. this bit must not be set, if xmfs is not enabled as an input. xmfs input selection is done by programming one of the transmit multifunction ports, using registers pc4(4:1).xpc(3:0). note: xmfs must not be used together with sypx on different multifunction ports. mode mode2 mode3 00 h 00 h 00 h signaling controller disabled rah(2:1) ral(2:1) fd h , ff h ff h , ff h compare register for receive address cleared rtr(4:1) ttr(4:1) tss2 tss3 all 00 h all 00 h 00 h 00 h no time slots selected table 54 initial values after reset and fmr1.pmod = 1 (t1/j1) (cont?d) register initiated value meaning falc ? 56 pef 2256 h/e operational description t1/j1 user?s manual 206 ds1.1, 2003-10-23 hardware description consequent actions to remote end and internal system depend on the activation procedure selected. note: read access to unused register addresses: value should be ignored. write access to unused register addresses: should be avoided, or set to 00 h in address range up to af h ; must be avoided in address range above af h if not defined elsewhere. all control registers (except xfifo, xs(12:1), cmdr, dec) are of type read/write table 55 initialization parameters (t1/j1) basic set up t1 j1 master clocking mode gcm(8:1) according to external mclk clock frequency t1/j1 mode select fmr1.pmod = 1, rc0.sjr = 0 fmr1.pmod = 1, rc0.sjr = 1 specification of line interface and clock generation lim0, lim1, xpm(2:0) line interface coding fmr0.xc(1:0), fmr0.rc(1:0) loss-of-signal detection/ recovery conditions pcd, pcr, lim1, lim2 system clocking and data rate sic1.ssc(1:0), sic1.ssd1, fmr1.ssd0, cmr1.irsp/ irsc/ixsp/ixsc channel translation mode fmr1.ctm transmit offset counters xc0.xco, xc1.xto receive offset counters rc0.rco, rc1.rto ais to system interface fmr2.dais/sais operational setup select framing fmr4.fm(1:0) framing additions fmr1.crc, fmr0.sraf synchronization mode fmr4.auto, fmr4.ssc(1:0), fmr2.mcsp, fmr2.ssp signaling mode fmr5.eibr, xc0.brm, mode, mode2, mode3, ccr1, ccr2, rah(2:1), ral(2:1) falc ? 56 pef 2256 h/e operational description t1/j1 user?s manual 207 ds1.1, 2003-10-23 hardware description specific t1/j1 initialization the following is a suggestion for a basic initialization to meet most of the t1/j1 requirements. depending on different applications and requirements any other initialization can be used. table 56 line interface initialization (t1/j1) register function fmr0.xc0/1 fmr0.rc0/1 lim1.drs ccb(3:1) sic3.cmi the falc ? 56 supports requirements for the analog line interface as well as the digital line interface. for the analog line interface the codes ami (with and without bit 7stuffing) and b8zs are supported. for the digital line interface modes (dual- or single-rail) the falc ? 56 supports ami (with and without bit 7 stuffing), b8zs (with and without b8zs precoding) and nrz. pcd = 0a h los detection after 176 consecutive ?zeros? (fulfills g.775/ telcordia (bellcore)/at&t) pcr = 15 h los recovery after 22 ?ones? in the pcd interval (fulfills g.775, bellcore/at&t). lim1.ril(2:0) =02 h los threshold of 0.6 v (fulfills g.775). gcr.sci = 1 additional recovery interrupts. help to meet alarm activation and deactivation conditions in time. lim2.los1 = 1 automatic pulse-density check on 15 consecutive zeros for los recovery condition (bellcore requirement) falc ? 56 pef 2256 h/e operational description t1/j1 user?s manual 208 ds1.1, 2003-10-23 hardware description table 57 framer initialization (t1/j1) register function t1 j1 fmr4.ssc1/0 selection of framing sync conditions fmr4.fm1/0 select framing format fmr2.axra = 1 the transmission of rai via the line interface is done automatically by the falc ? 56 in case of loss of frame alignment (frs0.lfa = 1). if framing has been reinstalled rai is automatically reset fmr4.auto = 1 automatic synchronization in case of definite framing candidate (frs0.fsrf). in case of multiple framing candidates and crc6 errors different resynchronization conditions can be programmed via fmr2.mcsp/ssp. rco.sjr 1) =1 fmr0.sraf = 0 xsw.xra = 1 1) remote alarm handling and crc6 calculation are commonly selected by rc0.sjr remote alarm handling via dl- channel according to itu-t jg.704 using pattern "1111111111111111" rco.sjr = 0 crc6 calculation without fs/ dl-bits rco.sjr = 1 crc6 calculation including fs/ dl-bits fmr4.auto = 1 automatic synchronization in case of definite framing candidate (frs0.fsrf). in case of multiple framing candidates and crc6 errors different resynchronization conditions can be programmed via fmr2.mcsp/ssp. fmr4.ssc1 = 1 fmr4.ssc0 = 1 fmr2.mcsp = 0 fmr2.ssp = 1 synchronization and resynchronization conditions, for details see register description falc ? 56 pef 2256 h/e operational description t1/j1 user?s manual 209 ds1.1, 2003-10-23 hardware description note: after the device initialization a software reset should be executed by setting of bits cmdr.xres/rres. table 58 hdlc controller initialization (t1/j1) mode = 88 h mode2= 88 h mode3= 88 h hdlc channel 1, 2, and 3receivers active on line side, no address comparison. ccr1 = 18 h ccr3= 08 h ccr4= 08 h enable signaling via ts(24:1), interframe time fill with continuous flags (channel 1). interframe time fill with continuous flags (channel 2). interframe time fill with continuous flags (channel 3). imr0.rme = 0 imr0.rpf = 0 imr1.xpr = 0 imr4.rme2=0 imr4.rpf2=0 imr5.xpr2=0 imr5.rme3=0 imr5.rpf3=0 imr5.xpr3=0 unmask interrupts for hdlc processor requests. rtr4.0 = 1 ttr4.0 = 1 tseo = 00 h tsbs1 = ff h tsbs2= ff h tsbs3= ff h tss2= 01 h tss3= 02 h select time slot 24 for hdlc data reception and transmission. even and odd frames are used for hdlc reception and transmission. select all bits of selected time slot (channel 1). select all bits of selected time slot (channel 2). select all bits of selected time slot (channel 3). select time slot 1 for hdlc channel 2. select time slot 2 for hdlc channel 3. table 59 initialization of the cas-br controller (t1/j1) fmr5.eibr = 1 enable cas-br mode send cas-br information stored in xs(12:1) imr1.case = 0 imr0.rsc = 0 enable interrupts which indicate the access to the xs(12:1) cas-br registers and any data change in rs(12:1) falc ? 56 pef 2256 h/e operational description t1/j1 user?s manual 210 ds1.1, 2003-10-23 hardware description 7.4 digital clock interface mode the falc ? 56 can be used to receive and transmit clock information instead of data . the configuration for this mode is 1.544 mhz input clock on rl1/rl2 1.544 mhz output clock on xl1/xl2 transmit clock referenced by sclkx (cmr1.dxss = 0) transmit pulse mask set to xmp0 = ff h , xpm1 = bd h , and xpm2 = 07 h 7.5 output signal tristate modes some output signals can be switched into tristate mode if unused or for wired-or configurations. see table 60 for more detail. table 60 output tristate programming (t1/j1) signal tristate mode selection note rclk pc5.crp = 0 internal pull-up active rdo rsig sic3.rtri = 1 during inactive channel phases only sec/fsc sic3.fsct = 1 b rpa pc1.rpc(3:0) = 1001 b internal pull-up active rpb pc2.rpc(3:0) = 1001 b internal pull-up active rpc pc3.rpc(3:0) = 1001 b internal pull-up active rpd pc4.rpc(3:0) = 1001 b internal pull-up active xpa pc1.xpc(3:0) = 1001 b internal pull-up active xpb pc2.xpc(3:0) = 1001 b internal pull-up active xpc pc3.xpc(3:0) = 1001 b internal pull-up active xpd pc4.xpc(3:0) = 1001 b internal pull-up active xl1 xl2 xpm2.xlt = 1 b or pc1.xpc(3:0) = 1000 b and xpa = high or pc2.xpc(3:0) = 1000 b and xpb = high or pc3.xpc(3:0) = 1000 b and xpc = high or pc4.xpc(3:0) = 1000 b and xpd = high d(15:0) wr =low falc ? 56 pef 2256 h/e signaling controller operating modes user?s manual 211 ds1.1, 2003-10-23 hardware description 8 signaling controlle r operating modes the three hdlc controllers can be programmed to operate in various modes, which are different in the treatment of the hdlc frame in receive direction. thus, the receive data flow and the address recognition features can be performed in a very flexible way, to satisfy almost any practical requirements. there are 4 different operating modes which can be set via the mode registers (mode, mode2 and mode3). if not mentioned otherwise, all functions described for hdlc channel 1 apply to channel 2 and 3 as well. 8.1 hdlc mode all frames with valid addresses are forwarded directly via the rfifo to the system memory. depending on the selected address mode, the falc ? 56 can perform a 1- or 2-byte address recognition (mode.mds0). if a 2-byte address field is selected, the high address byte is compared to the fixed value feh or fch (group address) as well as with two individually programmable values in rah1 and rah2 registers. according to the isdn lapd protocol, bit 1 of the high byte address is interpreted as command/response bit (c/r) and is excluded from the address comparison. similarly, two compare values can be programmed in special registers (ral1, ral2) for the low address byte. a valid address is recognized in case the high and low byte of the address field correspond to one of the compare values. thus, the falc ? 56 can be called (addressed) with 6 different address combinations. hdlc frames with address fields that do not match any of the address combinations, are ignored by the falc ? 56. in case of a 1-byte address, ral1 and ral2 are used as compare registers. the hdlc control field, data in the i-field and an additional status byte are temporarily stored in the rfifo. additional information can also be read from a special register (rsis). as defined by the hdlc protocol, the falc ? 56 performs the zero bit insertion/deletion (bit stuffing) in the transmit/receive data stream automatically. that means, it is guaranteed that at least one ?0? will appear after 5 consecutive ?1?s. 8.1.1 non-auto mode (mode.mds(2:1) = 01; mode2.mds22..21=01; mode3.mds32..31=01) characteristics: address recognition, flag- and crc generation/check, bit stuffing all frames with valid addresses are forwarded directly via the rfifo (rfifo2, rfifo3) to the system memory. falc ? 56 pef 2256 h/e signaling controller operating modes user?s manual 212 ds1.1, 2003-10-23 hardware description 8.1.2 transparent mode 1 (mode.mds(2:0) = 101; mode2.mds2(2:0)=101; mode3.mds3(2:0)=101) characteristics: address recognition, flag- and crc generation/check, bit stuffing only the high byte of a 2-byte address field is compared to registers rah(2:1). the whole frame excluding the first address byte is stored in rfifo (rfifo2, rfifo3). 8.1.3 transparent mode 0 (mode.mds(2:0) = 100; mode2.mds2(2:0)=100; mode3.mds3(2:0)=100) characteristics: flag- and crc generation/check, bit stuffing no address recognition is performed and each frame is stored in the rfifo (rfifo2, rfifo3). 8.1.4 ss7 support ss7 protocol is supported for channel 1 only by means of several hardware features as described in chapter 4.1.15.2 on page 78 and chapter 5.1.15.2 on page 139 . 8.1.5 receive data flow the following figure gives an overview of the management of the received hdlc frames in the different operating modes. falc ? 56 pef 2256 h/e signaling controller operating modes user?s manual 213 ds1.1, 2003-10-23 hardware description figure 80 hdlc receive data flow f0235 flag ctrl flag addr crc data rsis rsis rsis rsis rah1,2 ral1,2 2) 2) rah1,2 2) rah1,2 2) x 1) 1) 1) mode.mds(2:0) 0 1 1 non-auto/16 0 1 0 non-auto/8 1 0 1 transparent 1 1 0 0 transparent 0 description of symbols: compared with register stored in fifo or register 1) rfifo rfifo rfifo rfifo in case of 8-bit address the control field starts here 1) crc is optionally stored in rfifo of hdlc channel 1, 2 or 3 if ccr2.rcrc = 1 (channel 1) ccr3.rcrc2 = 1 (channel 2) ccr4.rcrc3 = 1 (channel 3) 2) address is optionally stored in rfifo of hdlc channel 1, 2 or 3 if ccr2.radd = 1 (channel 1) ccr3.radd2 = 1 (channel 2) ccr4.radd3 = 1 (channel 3) falc ? 56 pef 2256 h/e signaling controller operating modes user?s manual 214 ds1.1, 2003-10-23 hardware description 8.1.6 transmit data flow the frames can be transmitted as shown below. figure 81 hdlc transmit data flow transmitting an hdlc frame via register cmdr.xtf (or cmdr2.xtf2/cmdr3.xtf3 for channel 2/3), the address, the control fields and the data field have to be entered in the xfifo (xfifo2, xfifo3). if ccr2.xcrc (or ccr3.xcrc2/ccr4.xcrc3 for channel 2/3) is set, the crc checksum will not be generated internally. the checksum has to be provided via the transmit fifo (xfifo, xfifo2, xfifo3) as the last two bytes. the transmitted frame is closed automatically with a closing flag only. the falc ? 56 does not check whether the length of the frame, i.e. the number of bytes to be transmitted makes sense or not. 8.2 extended transparent mode characteristics: fully transparent in no hdlc mode, fully transparent data transmission/reception without hdlc framing is performed, i.e. without flag generation/recognition, crc generation/check, or bit stuffing. this feature can be profitably used e.g. for: specific protocol variations transmission of a bom frame (channel 1 only) test purposes data transmission is always performed out of the xfifo (xfifo2, xfifo3). in transparent mode, the receive data is shifted into the rfifo (rfifo2, rfifo3). note: if a 1-byte frame is sent in extended transparent mode, in addition to interrupt isr1.xpr (transmit pool ready) the interrupt isr1.xdu (transmit buffer underrun) is set and xfifo is blocked. control (xhf) frame hdlc transmit address flag xfifo addr ctrl flag data checkram itd06456 crc falc ? 56 pef 2256 h/e signaling controller operating modes user?s manual 215 ds1.1, 2003-10-23 hardware description 8.3 signaling controller functions 8.3.1 transparent transmission and reception when programmed in the extended transparent mode via the mode registers (mode.mds(2:0) = 111, mode2.mds2(2:0)=111, mode3.mds3(2:0)=111), the falc ? 56 performs fully transparent data transmission and reception without hdlc framing, i.e. without flag insertion and deletion crc generation and checking bit stuffing in order to enable fully transparent data transfer, bit mode.hrac (mode2.hrac2, mode3.hrac3) has to be set. received data is always shifted into rfifo (rfifo2, rfifo3). data transmission is always performed out of xfifo (xfifo2, xfifo3) by shifting the contents of xfifo into the outgoing data stream directly. transmission is initiated by setting cmdr.xtf (04 h ). a synchronization byte ff h is sent automatically before the first byte of the xfifo is transmitted. cyclic transmission (fully transparent) if the extended transparent mode is selected, the falc ? 56 supports the continuous transmission of the contents of the transmit fifos. after having written 1 to 32 bytes to xfifo (xfifo2, xfifo3), the command xrep&xtf (cmdr = 00100100 = 24 h ) forces the falc ? 56 to transmit the data stored in xfifo to the remote end repeatedly. note: the cyclic transmission continues until a reset command (cmdr.sres) is issued or with resetting of cmdr.xrep, after which continuous ?1?s are transmitted. during cyclic transmission the xrep-bit has to be set with every write operation to cmdr. the same handling applies to cmdr2 and cmdr3 for hdlc channels 2 an 3. 8.3.2 crc on/off features as an option in hdlc mode the internal handling of the received and transmitted crc checksum can be influenced via control bits ccr2.rcrc and ccr2.xcrc (channel 2: ccr3.rcrc2, ccr3.xcrc2, channel 3: ccr4.rcrc3, ccr4.xcrc3). receive direction the received crc checksum is always assumed to be in the 2 last bytes of a frame (crc-itu), immediately preceding a closing flag. if ccr2.rcrc is set, the received crc checksum is written to rfifo where it precedes the frame status byte (contents of register rsis). the received crc checksum is additionally checked for correctness. if falc ? 56 pef 2256 h/e signaling controller operating modes user?s manual 216 ds1.1, 2003-10-23 hardware description hdlc mode is selected, the limits for ?valid frame? check are modified (refer to description of bit rsis.vfr). transmit direction if ccr2.xcrc is set, the crc checksum is not generated internally. the checksum has to be provided via the transmit fifo (xfifo) as the last two bytes. the transmitted frame is closed automatically by a closing flag only. the falc ? 56 does not check whether the length of the frame, i.e. the number of bytes to be transmitted is valid or not. 8.3.3 receive address pushed to rfifo the address field of received frames can be pushed to the receive fifos (first one or two bytes of a frame). this function is used together with extended address recognition. it is enabled by setting control bit ccr2.radd (ccr3.radd2, ccr4.radd3). 8.3.4 hdlc data transmission in transmit direction 2 32 byte fifo buffers are provided for each hdlc channel. after checking the xfifo status by polling bit sis.xfw (sis2.xfw2, sis3,xfw3) or after an interrupt isr1.xpr (isr5.xpr2, isr5.xpr3, transmit pool ready), up to 32 bytes can be entered by the cpu to the xfifos. the transmission of a frame can be started by issuing a xtf or xhf command via the command registers. if the transmit command does not include an end of message indication (cmdr.xme, cmdr3.xme2, cmdr4.xme3), the falc ? 56 will repeatedly request for the next data block by means of an xpr interrupt as soon as no more than 32 bytes are stored in the xfifo, i.e. a 32-byte pool is accessible to the cpu. this process is repeated until the cpu indicates the end of message by xme command, after which frame transmission is finished correctly by appending the crc and closing flag sequence. consecutive frames can share a flag, or can be transmitted as back-to- back frames, if service of the xfifos is fast enough. in case no more data is available in the xfifos prior to the arrival of xme, the transmission of the frame is terminated with an abort sequence and the cpu is notified by interrupt isr1.xdu (isr4.xdu2, isr5.xdu 3). the frame can be aborted by software using cmdr.sres (cmdr3.sres2, cmdr4.sres3). the data transmission sequence, from the cpu?s point of view, is outlined in figure 82 . falc ? 56 pef 2256 h/e signaling controller operating modes user?s manual 217 ds1.1, 2003-10-23 hardware description figure 82 interrupt driven data transmission (flow diagram) the activities at both serial and cpu interface during frame transmission (supposed frame length = 70 bytes) shown in figure 83 . figure 83 interrupt driven transmission example itd08565 start transmit pool ready ? xpr interrupt, xfw bit in sis register or =1 write data (up to 32 to xfifo bytes) y message end of ? xtf/xhf command n y n command xtf/xhf end + xme itd10971 wr xfifo 32 bytes system interface interface cpu alls xpr xhf + xme 6 bytes wr xfifo xpr xpr xhf 32 bytes wr xfifo command xhf transmit frame (70 bytes) 32 32 6 r falc falc ? 56 pef 2256 h/e signaling controller operating modes user?s manual 218 ds1.1, 2003-10-23 hardware description 8.3.5 hdlc data reception 2 32 byte fifo buffers are also provided in receive direction for each hdlc channel. there are different interrupt indications concerned with the reception of data: rpf (rpf2, rpf3, receive pool full) interrupt, indicating that a 32-byte block of data can be read from rfifo (rfifo2, rfifo3) and the received message is not yet complete. rme (rme2, rme3, receive message end) interrupt, indicating that the reception of one message is completed. the following figure gives an example of a reception sequence, assuming that a ?long? frame (66 bytes) followed by two short frames (6 bytes each) are received. figure 84 interrupt driven reception sequence example 8.3.6 s a -bit access (e1) the falc ? 56 supports the s a -bit signaling of time slot 0 of every other frame as follows: access via registers rsw/xsw access via registers rsa(8:4)/xsa(8:4) capable of storing the information for a complete multiframe access via the 64 byte deep receive/transmit fifo of the integrated signaling controller (hdlc channel 1 only). this s a -bit access gives the opportunity to transmit/ receive a transparent bit stream as well as hdlc frames where the signaling controller automatically processes the hdlc protocol. enabling is done by setting of bit ccr1.eits and resetting of registers ttr(4:1), rtr(4:1) and fmr1.ensa. data written to the xfifo will be transmitted subsequently in the s a -bit positions itd10972 rd rfifo 32 bytes rmc receive frame 1 (66 bytes) 32 6 rpf rpf 32 2 32 bytes rd rfifo rmc rme rd status rd2 bytes rme rmc rd6 bytes rd status rmc rme rmc rd status rd6 bytes 6 rf2 rf3 falc r interface cpu interface system falc ? 56 pef 2256 h/e signaling controller operating modes user?s manual 219 ds1.1, 2003-10-23 hardware description defined by register xc0.sa8e to sa84e and the corresponding bits of tswm.tsa(8:4). any combination of s a -bits can be selected. after the data has been sent out completely an ?all ones? or flags (ccr1.itf) is transmitted. the continuous transmission of a transparent bit stream, which is stored in the xfifo, can be enabled. with the setting of bit mode.hrac the received s a -bits can be forwarded to the receive fifo. the access to and from the fifos is supported by isr0.rme/rpf and isr1.xpr/ als. 8.3.7 bit oriented message mode (t1/j1) the falc ? 56 supports signaling and maintenance functions for t1/j1 primary rate interfaces using the extended super frame format. the hdlc channel 1 of the device supports the dl-channel protocol for esf format according to t1.403-1989 ansi or to at&t tr54016 specification. the hdlc and bit oriented message (bom) -receiver can be switched on/off independently. if the falc ? 56 is used for hdlc formats only, the bom receiver has to be switched off. if hdlc and bom receiver has been switched on (mode.hrac/brac), an automatic switching between hdlc and bom mode is enabled. storing of received dl-bit information in the rfifo of the signaling controller and transmitting the xfifo contents in the dl-bit positions is enabled by ccr1.edlx/ eits = 10. after hardware-reset (pin res low) or software-reset (cmdr.rres = 1) the falc ? 56 operates in hdlc mode. if eight or more consecutive ones are detected, the bom mode is entered. upon detection of a flag in the data stream, the falc ? 56 switches back to hdlc mode. operating in bom mode, the falc ? 56 is able to receive an hdlc frame immediately, i.e. without any preceding flags. in bom mode, the following byte format is assumed (the left most bit is received first; 111111110xxxxxx0). the falc ? 56 uses the ff h byte for synchronization, the next byte is stored in rfifo (first bit received: lsb) if it starts and ends with a ?0?. bytes starting and ending with a ?1? are not stored. if there are no 8 consecutive ones detected within 32 bits, an interrupt is generated. however, byte sampling is not stopped. falc ? 56 pef 2256 h/e signaling controller operating modes user?s manual 220 ds1.1, 2003-10-23 hardware description byte sampling in bom mode (t1/j1) a) b) three different bom reception modes can be programmed (ccr1.brm, ccr2.rbfe). 10 byte packets: ccr1.brm = 0 after storing 10 bytes in rfifo the receive status byte marking a bom frame (rsis.hfr) is added as the eleventh byte and an interrupt (isr0.rme) is generated. the sampling of data bytes continues and interrupts are generated every 10 bytes until an hdlc flag is detected. continuous reception: ccr1.brm = 1 interrupts are generated every 32 (16, 4, 2) bytes. after detecting an hdlc flag, byte sampling is stopped, the receive status byte is stored in rfifo and an rme interrupt is generated. reception with enabled bom filter: ccr2.rbfe = 1 the bom receiver will only accept bom frames after detecting 7 out of 10 equal bom pattern. the bom pattern is stored in the rfifo adding a receive status byte, marking a bom frame (rsis.hfr) and generating an interrupt status isr0.rme. the current state of the bom receiver is indicated in register sis.ivb. when the valid bom pattern disappears an interrupt isr0.biv is generated. the user can switch between these modes at any time. byte sampling can be stopped by deactivating the bom receiver (mode.brac). in this case the receive status byte is added, an interrupt is generated and hdlc mode is entered. whether the falc ? 56 operates in hdlc or bom mode are checked by reading the signaling status register (sis.bom). 1111 1111 1111 0011 0100 1111 1111 0011 0100 1110 1111 0011 0100 1101 1111 sync not stored new sync 1.byte stored 1.corrupted sync 2.byte stored 2.corrupted sync corrupted sync 1111 1111 0111 0110 1101 1111 0111 0110 1111 1111 0111 0110 0111 1111 sync 1.byte stored 1.corrupted byte 2.byte stored 2.sync 3.byte stored 3.corrupted sync falc ? 56 pef 2256 h/e signaling controller operating modes user?s manual 221 ds1.1, 2003-10-23 hardware description 8.3.8 data link access in esf/f72 format (t1/j1) the falc ? 56 supports the dl-channel protocol using the esf or f72 (slc96) format as follows (hdlc channel 1 only): sampling of dl-bits is done on a multiframe basis and stored in the registers rdl(3:1). a receive multiframe begin interrupt is provided to read the received data dl-bits. the contents of registers xdl(3:1) is subsequently sent out on the transmit multiframe basis if it is enabled via fmr1.edl. a transmit multiframe begin interrupt requests for writing new information to the dl-bit registers. if enabled via ccr1.edlx/eits = 10, the dl-bit information is stored in the receive fifo of the signaling controller. the dl-bits stored in the xfifo are inserted into the outgoing data stream. if ccr1.edlx is cleared, a hdlc frame or a transparent frame can be sent or received via the rfifo/xfifo. falc ? 56 pef 2256 h/e user?s manual 222 ds1.1, 2003-10-23 hardware description register description due to the different device function is e1 and t1/j1 mode, several registers and register bits have dedicated functions according to the selected operation mode. to maintain easy readability this chapter is divided into separate e1 and t1/j1 sections. please choose the correct description according to your application (e1 or t1/j1). falc ? 56 pef 2256 h/e e1 registers user?s manual 223 ds1.1, 2003-10-23 hardware description 9 e1 registers 9.1 e1 control register addresses table 61 e1 control register address arrangement address register type comment page 00 xfifo w transmit fifo 227 01 xfifo w transmit fifo 227 02 cmdr w command register 227 03 mode r/w mode register 229 04 rah1 r/w receive address high 1 230 05 rah2 r/w receive address high 2 230 06 ral1 r/w receive address low 1 230 07 ral2 r/w receive address low 2 231 08 ipc r/w interrupt port configuration 231 09 ccr1 r/w common configuration register 1 232 0a ccr2 r/w common configuration register 2 234 0c rtr1 r/w receive time slot register 1 235 0d rtr2 r/w receive time slot register 2 235 0e rtr3 r/w receive time slot register 3 235 0f rtr4 r/w receive time slot register 4 235 10 ttr1 r/w transmit time slot register 1 236 11 ttr2 r/w transmit time slot register 2 236 12 ttr3 r/w transmit time slot register 3 236 13 ttr4 r/w transmit time slot register 4 236 14 imr0 r/w interrupt mask register 0 237 15 imr1 r/w interrupt mask register 1 237 16 imr2 r/w interrupt mask register 2 237 17 imr3 r/w interrupt mask register 3 237 18 imr4 r/w interrupt mask register 4 237 19 imr5 r/w interrupt mask register 5 237 1b ierr r/w single bit error insertion register 237 1c fmr0 r/w framer mode register 0 238 falc ? 56 pef 2256 h/e e1 registers user?s manual 224 ds1.1, 2003-10-23 hardware description 1d fmr1 r/w framer mode register 1 240 1e fmr2 r/w framer mode register 2 242 1f loop r/w channel loop-back 243 20 xsw r/w transmit service word 244 21 xsp r/w transmit spare bits 245 22 xc0 r/w transmit control 0 246 23 xc1 r/w transmit control 1 247 24 rc0 r/w receive control 0 248 25 rc1 r/w receive control 1 249 26 xpm0 r/w transmit pulse mask 0 251 27 xpm1 r/w transmit pulse mask 1 251 28 xpm2 r/w transmit pulse mask 2 251 29 tswm r/w transparent service word mask 252 2b idle r/w idle channel code 253 2c xsa4 r/w transmit s a 4-bit register 254 2d xsa5 r/w transmit s a 5-bit register 254 2e xsa6 r/w transmit s a 6-bit register 254 2f xsa7 r/w transmit s a 7-bit register 254 30 xsa8 r/w transmit s a 8-bit register 254 31 fmr3 r/w framer mode register 3 255 32 icb1 r/w idle channel register 1 256 33 icb2 r/w idle channel register 2 256 34 icb3 r/w idle channel register 3 256 35 icb4 r/w idle channel register 4 256 36 lim0 r/w line interface mode 0 257 37 lim1 r/w line interface mode 1 258 38 pcd r/w pulse count detection 260 39 pcr r/w pulse count recovery 260 3a lim2 r/w line interface mode 2 261 3b lcr1 r/w loop code register 1 262 table 61 e1 control register address arrangement (cont?d) address register type comment page falc ? 56 pef 2256 h/e e1 registers user?s manual 225 ds1.1, 2003-10-23 hardware description 3c lcr2 r/w loop code register 2 264 3d lcr3 r/w loop code register 3 264 3e sic1 r/w system interface control 1 265 3f sic2 r/w system interface control 2 266 40 sic3 r/w system interface control 3 267 44 cmr1 r/w clock mode register 1 269 45 cmr2 r/w clock mode register 2 270 46 gcr r/w global configuration register 273 47 esm r/w errored second mask 274 45 cmr2 r/w clock mode register 2 270 48 cmr3 r/w clock mode register 3 274 70 xs1 w transmit cas register 1 276 71 xs2 w transmit cas register 2 276 72 xs3 w transmit cas register 3 276 73 xs4 w transmit cas register 4 276 74 xs5 w transmit cas register 5 276 75 xs6 w transmit cas register 6 276 76 xs7 w transmit cas register 7 276 77 xs8 w transmit cas register 8 276 78 xs9 w transmit cas register 9 276 79 xs10 w transmit cas register 10 276 7a xs11 w transmit cas register 11 276 7b xs12 w transmit cas register 12 276 7c xs13 w transmit cas register 13 276 7d xs14 w transmit cas register 14 276 7e xs15 w transmit cas register 15 276 7f xs16 w transmit cas register 16 276 80 pc1 r/w port configuration 1 277 81 pc2 r/w port configuration 2 277 82 pc3 r/w port configuration 3 277 table 61 e1 control register address arrangement (cont?d) address register type comment page falc ? 56 pef 2256 h/e e1 registers user?s manual 226 ds1.1, 2003-10-23 hardware description 83 pc4 r/w port configuration 4 277 84 pc5 r/w port configuration 5 280 85 gpc1 r/w global port configuration 1 281 86 pc6 r/w port configuration 6 282 87 cmdr2 w command register 2 283 88 cmdr3 w command register 3 283 89 cmdr4 w command register 4 284 8b ccr3 r/w common control register 3 285 8c ccr4 r/w common control register 4 287 8d ccr5 r/w common control register 5 288 8e mode2 r/w mode register 2 289 8f mode3 r/w mode register 3 290 92 gcm1 r/w global counter mode 1 291 93 gcm2 r/w global counter mode 2 291 94 gcm3 r/w global counter mode 3 291 95 gcm4 r/w global counter mode 4 291 96 gcm5 r/w global counter mode 5 292 97 gcm6 r/w global counter mode 6 292 98 gcm7 r/w global counter mode 7 292 99 gcm8 r/w global counter mode 8 292 9c xfifo2 w transmit fifo 2 293 9d xfifo2 w transmit fifo 2 293 9e xfifo3 w transmit fifo 3 293 9f xfifo3 w transmit fifo 3 293 a0 tseo r/w time slot even/odd select 294 a1 tsbs1 r/w time slot bit select 1 295 a2 tsbs2 r/w time slot bit select 2 295 a3 tsbs3 r/w time slot bit select 3 296 a4 tss2 r/w time slot select 2 296 a5 tss3 r/w time slot select 3 297 table 61 e1 control register address arrangement (cont?d) address register type comment page falc ? 56 pef 2256 h/e e1 registers user?s manual 227 ds1.1, 2003-10-23 hardware description after reset all control registers except the xfifo and xs(16:1) are initialized to defined values. unused bits have to be cleared (logical "0"). note: read access to unused register addresses: value should be ignored. write access to unused register addresses: should be avoided, or set to 00 h in address range up to af h ; must be avoided in address range above af h if not defined elsewhere 9.2 detailed description of e1 control registers transmit fifo - hdlc channel 1 (write) writing data to xfifo of hdlc channel 1 can be done in 8-bit (byte) or 16-bit (word) access. the lsb is transmitted first. up to 32 bytes/16 words of transmit data can be written to the xfifo following a xpr interrupt. command register (write) value after reset: 00 h rmc receive message complete - hdlc channel 1 confirmation from cpu to falc ? 56 that the current frame or data block has been fetched following a rpf or rme interrupt, thus the occupied space in the rfifo can be released. if rmc is given while rfifo is already cleared, the next incoming data block is cleared instantly, although interrupts are generated. rres receiver reset a8 tpc0 r/w test pattern control register 0 297 af glc1 r/w global line control register 1 298 70 xfifo xf7 xf0 (00) xfifo xf15 xf8 (01) 70 cmdr rmc rres xrep xres xhf xtf xme sres (02) table 61 e1 control register address arrangement (cont?d) address register type comment page falc ? 56 pef 2256 h/e e1 registers user?s manual 228 ds1.1, 2003-10-23 hardware description the receive line interface except the clock and data recovery unit (dpll), the receive framer, the one-second timer and the receive signaling controller are reset. however the contents of the control registers is not deleted. xrep transmission repeat - hdlc channel 1 if xrep is set together with xtf (write 24 h to cmdr), the falc ? 56 repeatedly transmits the contents of the xfifo (1 to 32 bytes) without hdlc framing fully transparently, i.e. without flag, crc. the cyclic transmission is stopped with a sres command or by resetting xrep. note:during cyclic transmission the xrep-bit has to be set with every write operation to cmdr. xres transmitter reset the transmit framer and transmit line interface excluding the system clock generator and the pulse shaper are reset. however the contents of the control registers is not deleted. xhf transmit hdlc frame - hdlc channel 1 after having written up to 32 bytes to the xfifo, this command initiates the transmission of a hdlc frame. xtf transmit transparent frame - hdlc channel 1 initiates the transmission of a transparent frame without hdlc framing. xme transmit message end - hdlc channel 1 indicates that the data block written last to the transmit fifo completes the current frame. the falc ? 56 can terminate the transmission operation properly by appending the crc and the closing flag sequence to the data. sres signaling transmitter reset - hdlc channel 1 the transmitter of the signaling controller is reset. xfifo is cleared of any data and an abort sequence (seven 1's) followed by interframe time fill is transmitted. in response to sres a xpr interrupt is generated. this command can be used by the cpu to abort a frame currently in transmission. note: the maximum time between writing to the cmdr register and the execution of the command takes 2.5 periods of the current system data rate. therefore, if the cpu operates with a very falc ? 56 pef 2256 h/e e1 registers user?s manual 229 ds1.1, 2003-10-23 hardware description high clock rate in comparison with the falc ? 56's clock, it is recommended that bit sis.cec should be checked before writing to the cmdr register to avoid any loss of commands. note: if sclkx is used to clock the transmission path, commands to the hdlc transmitter should only be sent while this clock is available. if sclkx is missing, the command register is blocked after an hdlc command is given. mode register (read/write) value after reset: 00 h mds(2:0) mode select - hdlc channel 1 the operating mode of the hdlc controller is selected. 000 = reserved 001 = signaling system 7 (ss7) support 1) 010 = one-byte address comparison mode (ral1,2) 011 = two-byte address comparison mode (rah1,2 and ral1,2) 100 = no address comparison 101 = one-byte address comparison mode (rah1,2) 110 = reserved 111 = no hdlc framing mode hrac receiver active - hdlc channel 1 switches the hdlc receiver to operational or inoperational state. 0 = receiver inactive 1 = receiver active div data inversion - hdlc channel 1 setting this bit inverts the internal generated hdlc channel 1 data stream. 0 = normal operation, hdlc data stream not inverted 1 = hdlc data stream inverted 70 mode mds2 mds1 mds0 hrac div hdlci (03) 1) ccr2.radd must be set, if ss7 mode is selected falc ? 56 pef 2256 h/e e1 registers user?s manual 230 ds1.1, 2003-10-23 hardware description hdlci inverse hdlc operation - hdlc channel 1 setting this bit selects the hdlc channel 1 operation mode. 0 = normal operation, hdlc attached to line side 1 = inverse operation, hdlc attached to system side and receive line hdlc data is ignored. hdlc data is received on xdi and stored in rfifo and is transmitted from xfifo to rdo. transmit time slot configuration is done in rtr(4:1), receive time slot configurarion is done in ttr(4:1). receive address byte high register 1 (read/write) value after reset: fd h in operating modes that provide high byte address recognition, the high byte of the received address is compared to the individually programmable values in rah1 and rah2. the address registers are used by all hdlc channels in common. rah1 value of the first individual high address byte bit 1 (c/r-bit) is excluded from address comparison. receive address byte high register 2 (read/write) value after reset: ff h rah2 value of second individual high address byte receive address byte low register 1 (read/write) value after reset: ff h ral1 value of first individual low address byte 70 rah1 0 (04) 70 rah2 (05) 70 ral1 (06) falc ? 56 pef 2256 h/e e1 registers user?s manual 231 ds1.1, 2003-10-23 hardware description receive address byte low register 2 (read/write) value after reset: ff h ral2 value of the second individually programmable low address byte. interrupt port configuration (read/write) value after reset: 00 h note:unused bits have to be cleared. ssyf select sync frequency only applicable in master mode (lim0.mas = 1) and bit cmr2.dcf is cleared. 0 = reference clock on port sync is 2.048 mhz 1 = reference clock on port sync is 8 khz ic0, ic1 interrupt port configuration these bits define the function of the interrupt output stage (pin int): 70 ral2 (07) 70 ipc ssyf ic1 ic0 (08) ic1 ic0 function x 0 1 0 1 1 open drain output push/pull output, active low push/pull output, active high falc ? 56 pef 2256 h/e e1 registers user?s manual 232 ds1.1, 2003-10-23 hardware description common configuration register 1 (read/write) value after reset: 00 h xts16ra send remote alarm in time slot 16 sending of remote alarm in time slot 16 towards remote end by setting bit "y" in the cas multiframe alignment word. if xs registers are used for cas (instead of xsig), bit xs1.2 ("y") is logically ored with xts16ra. if xsig is used for cas, y-data received on xsig is logically ored with xts16ra. 0 = no remote alarm insertion 1 = remote alarm insertion casm cas synchronization mode determines the synchronization mode of the channel associated signaling multiframe alignment. 0 = synchronization is done in accordance to itu-t g. 732 1 = synchronization is established when two consecutively correct multiframe alignment pattern are found. eits enable internal time slot 0 to 31 signaling 0 = internal signaling in time slots 0 to 31 defined by registers rtr(4:1) or ttr(4:1) is disabled. 1 = internal signaling in time slots 0 to 31 defined by registers rtr(4:1) or ttr(4:1) is enabled. itf interframe time fill determines the idle (= no data to be sent) state of the transmit data coming from the signaling controller. 0 = continuous logical "1" is output 1 = continuous flag sequences are output ("01111110" bit patterns) xmfa transmit multiframe aligned determines the synchronization between the framer and the corresponding signaling controller. 0 = the contents of the xfifo is transmitted without multiframe alignment. 70 ccr1 xts16ra casm eits itf xmfa rft1 rft0 (09) falc ? 56 pef 2256 h/e e1 registers user?s manual 233 ds1.1, 2003-10-23 hardware description 1 = the contents of the xfifo is transmitted multiframe aligned. the first byte in xfifo is transmitted in the first time slot selected by ttr(4:1) and so on. after reception of a complete multiframe in the time slot mode (rtr(4:1)) an isr0.rme interrupt is generated, if no hdlc mode is enabled in s a -bit access mode xmfa is not valid. note: during the transmission of the xfifo content, the sypx or xmfs interval time should not be changed, otherwise the xfifo data has to be retransmitted. rft(1:0) rfifo threshold level - hdlc channel 1 the size of the accessible part of rfifo can be determined by programming these bits. the number of valid bytes after a rpf interrupt is given in the following table: the value of rft1, 0 can be changed dynamically. ? if reception is not running or ? after the current data block has been read, but before the command cmdr.rmc is issued (interrupt controlled data transfer). note: it is seen that changing the value of rft1, 0 is possible even during the reception of one frame. the total length of the received frame can be always read directly in rbcl, rbch after a rpf interrupt, except when the threshold is increased during reception of that frame. the real length can then be inferred by noting which bit positions in rbcl are reset by a rmc command (see table below): rft1 rft0 size of accessible part of rfifo 0 0 1 1 0 1 0 1 32 bytes (reset value) 16 bytes 4 bytes 2 bytes rft1 rft0 bit positions in rbcl reset by a cmdr.rmc command 0 0 1 1 0 1 0 1 rbc(4:0) rbc(3:0) rbc(1:0) rbc0 falc ? 56 pef 2256 h/e e1 registers user?s manual 234 ds1.1, 2003-10-23 hardware description common configuration register 2 (read/write) value after reset: 00 h note: unused bits have to be cleared. radd receive address pushed to rfifo - hdlc channel 1 if this bit is set, the received hdlc address information (1 or 2 bytes, depending on the address mode selected by mode.mds0) is pushed to rfifo. this function is applicable in non-auto mode and transparent mode 1. radd must be set, if ss7 mode is selected. rcrc receive crc on/off - hdlc channel 1 only applicable in non-auto mode. if this bit is set, the received crc checksum is written to rfifo (crc-itu-t: 2 bytes). the checksum, consisting of the 2 last bytes in the received frame, is followed by the status information byte (contents of register rsis). the received crc checksum is additionally checked for correctness. if non-auto mode is selected, the limits for ?valid frame? check are modified (refer to rsis.vfr). xcrc transmit crc on/off - hdlc channel 1 if this bit is set, the crc checksum is not generated internally. it has to be written to the transmit fifo as the last two bytes. the transmitted frame is closed automatically with a closing flag. note: the falc ? 56 does not check whether the length of the frame, i.e. the number of bytes to be transmitted makes sense or not. 70 ccr2 radd rcrc xcrc (0a) falc ? 56 pef 2256 h/e e1 registers user?s manual 235 ds1.1, 2003-10-23 hardware description receive time slot register 1 to 4 (read/write) value after reset: 00 h , 00 h , 00 h , 00 h ts(31:0) time slot these bits define the received time slots on the system highway port rdo to be extracted to rfifo and marked. additionally these registers control the rsigm marker which can be forced high during the corresponding time slots independently of bit ccr1.eits. a one in the rtr(4:1) bits samples the corresponding time slots and send their data to the rfifo of the signaling controller if bit ccr1.eits is set. assignments: ts0 time slot 0 ... ts31 time slot 31 0 =the corresponding time slot is not extracted and stored into the rfifo. 1 = the contents of the selected time slot is stored in the rfifo. although the idle time slots can be selected. this function is activated, if bit ccr1.eits is set. the corresponding time slot is forced high on marker pin rsigm. 70 rtr1 ts0 ts1 ts2 ts3 ts4 ts5 ts6 ts7 (0c) rtr2 ts8 ts9 ts10 ts11 ts12 ts13 ts14 ts15 (0d) rtr3 ts16 ts17 ts18 ts19 ts20 ts21 ts22 ts23 (0e) rtr4 ts24 ts25 ts26 ts27 ts28 ts29 ts30 ts31 (0f) falc ? 56 pef 2256 h/e e1 registers user?s manual 236 ds1.1, 2003-10-23 hardware description transmit time slot register 1 to 4 (read/write) value after reset: 00 h , 00 h , 00 h , 00 h ts(31:0) time slot these bits define the transmit time slots on the system highway to be inserted. additionally these registers control the xsigm marker which can be forced high during the corresponding time slots independently of bit ccr1.eits. a one in the ttr(4:1) bits inserts the corresponding time slot sourced by the xfifo in the data received on pin xdi, if bit ccr1.eits is set. if sic3.ttrf is set and ccr1.eits is cleared insertion of data received on port xsig is controlled by this registers. assignments: ts0 time slot 0 ... ts31 time slot 31 0 = the selected time slot is not inserted into the outgoing data stream. 1 = the contents of the selected time slot is inserted into the outgoing data stream from xfifo. this function is active only if bit ccr1.eits is set. the corresponding time slot is forced high on marker pin xsigm. 70 ttr1 ts0 ts1 ts2 ts3 ts4 ts5 ts6 ts7 (10) ttr2 ts8 ts9 ts10 ts11 ts12 ts13 ts14 ts15 (11) ttr3 ts16 ts17 ts18 ts19 ts20 ts21 ts22 ts23 (12) ttr4 ts24 ts25 ts26 ts27 ts28 ts29 ts30 ts31 (13) falc ? 56 pef 2256 h/e e1 registers user?s manual 237 ds1.1, 2003-10-23 hardware description interrupt mask register 0 to 5 (read/write) value after reset: ff h , ff h , ff h , ff h , ff h imr(5:0) interrupt mask register each interrupt source can generate an interrupt signal on port int (characteristics of the output stage are defined by register ipc). a ?1? in a bit position of imr(5:0) sets the mask active for the interrupt status in isr(5:0). masked interrupt statuses neither generate a signal on int, nor are they visible in register gis. moreover, they are - not displayed in the interrupt status register if bit gcr.vis is cleared - displayed in the interrupt status register if bit gcr.vis is set note:after reset, all interrupts are dis abled. single bit defect insertion register (read/write) value after reset: 00 h after setting the corresponding bit, the selected defect is inserted into the transmit data stream at the next possible position. after defect insertion is completed, the bit is reset automatically. ifase insert single fas defect imfe insert single multiframe defect icrce insert single crc defect icase insert single cas defect ipe insert single prbs defect 70 imr0 rme rfs t8ms rmb casc crc4 sa6sc rpf (14) imr1 llbsc rdo alls xdu xmb suex xlsc xpr (15) imr2 far lfa mfar t400ms ais los rar ra (16) imr3 es sec lmfa16 ais16 ra16 rsn rsp (17) imr4 xsp xsn rme2 rfs2 rdo2 alls2 xdu2 rpf2 (18) imr5 xpr2 xpr3 rme3 rfs3 rdo3 alls3 xdu3 rpf3 (19) ierr ifase imfe icrce icase ipe ibv (1b) falc ? 56 pef 2256 h/e e1 registers user?s manual 238 ds1.1, 2003-10-23 hardware description ibv insert bipolar violation note:except for crc defects, crc checksum calculation is done after defect insertion. framer mode register 0 (read/write) value after reset: 00 h xc(1:0) transmit code serial line code for the transmitter, independent of the receiver. 00 = nrz (optical interface) 01 = cmi (1t2b+hdb3), (optical interface) 10 = ami (ternary or digital dual-rail interface) 11 = hdb3 code (ternary or digital dual-rail interface) after changing xc(1:0), a transmitter software reset is required (cmdr.xres = 1). rc(1:0) receive code serial line code for the receiver, independent of the transmitter. 00 = nrz (optical interface) 01 = cmi (1t2b+hdb3), (optical interface) 10 = ami (ternary or digital dual-rail interface) 11 = hdb3 code (ternary or digital dual-rail interface) after changing rc(1:0), a receiver software reset is required (cmdr.rres = 1). exze extended hdb3 error detection selects error detection mode. 0 = only double violations are detected. 1 = extended code violation detection: 0000 strings are detected additionally. incrementing of the code violation counter cvc is done after receiving four zeros. errors are indicated by frs1.exzd = 1. 70 fmr0 xc1 xc0 rc1 rc0 exze alm frs sim (1c) falc ? 56 pef 2256 h/e e1 registers user?s manual 239 ds1.1, 2003-10-23 hardware description alm alarm mode selects the ais alarm detection mode. 0 = the ais alarm is detected according to ets300233. detection: an ais alarm is detected if the incoming data stream contains less than 3 zeros within a period of 512 bits and a loss of frame alignment is indicated. recovery: the alarm is cleared if 3 or more zeros within 512 bits are detected or the fas word is found. 1 = the ais alarm is detected according to itu-t g.775 detection: an ais alarm is detected if the incoming data stream contains less than 3 zeros in each doubleframe period of two consecutive doubleframe periods (1024 bits). recovery: the alarm is cleared if 3 or more zeros are detected within two consecutive doubleframe periods. frs force resynchronization a transition from low to high initiates a resynchronization procedure of the pulse frame and the crc-multiframe (if enabled by bit fmr2.rfs1) starting directly after the old framing candidate. sim alarm simulation 0 = normal operation. 1 = initiates internal error simulation of ais, loss-of-signal, loss of synchronization, remote alarm, slip, framing errors, crc errors, and code violations. the error counters fec, cvc, cec1 are incremented. sim has to be held stable at high or low level for at least one receive clock period before changing it again. falc ? 56 pef 2256 h/e e1 registers user?s manual 240 ds1.1, 2003-10-23 hardware description framer mode register 1 (read/write) value after reset: 00 h mfcs multiframe force resynchronization only valid if crc multiframe format is selected (fmr2.rfs(1:0) = 10). a transition from low to high initiates the resynchronization procedure for crc-multiframe alignment without influencing doubleframe synchronous state. in case, ?automatic force resynchronization? (fmr1.afr) is enabled and multiframe alignment cannot be regained, a new search of doubleframe (and crc multiframe) is automatically initiated. afr automatic force resynchronization only valid if crc multiframe format is selected (fmr2.rfs(1:0) = 10). if this bit is set, a search of doubleframe alignment is automatically initiated if two multiframe patterns with a distance of n 2 ms have not been found within a time interval of 8 ms after doubleframe alignment has been regained or command fmr1.mfcs has been issued. ensa enable s a -bit access through register xsa4-8 only applicable if fmr1.xfs is set. 0 = normal operation. the s a -bit information is taken from bits xsw.xy(4:0) and written to bits rsw.ry(4:0). 1= s a -bit register access. the s a -bit information is taken from the registers xsa(8:4). in addition, the received information is written to registers rsa(8:4). transmitting of the contents of registers xsa(8:4) is disabled if one of time slot 0 transparent modes is enabled (xsp.tt0 or tswm.sa(8:4)). 70 fmr1 mfcs afr ensa pmod xfs ecm ssd0 xais (1d) falc ? 56 pef 2256 h/e e1 registers user?s manual 241 ds1.1, 2003-10-23 hardware description pmod pcm mode for e1 application this bit must be set low. switching from e1 to t1 or vice versa the device needs up to 20 s to settle up to the internal clocking. 0 = pcm 30 or e1 mode. 1 = pcm 24 or t1/j1 mode (see rc0.sjr for t1/j1 selection). xfs transmit framing select selection of the transmit framing format can be done independently of the receive framing format. 0 = doubleframe format enabled. 1 = crc4-multiframe format enabled. ecm error counter mode the function of the error counters is determined by this bit. 0 = before reading an error counter the corresponding bit in the disable error counter register (dec) has to be set. in 8 bit access the low byte of the error counter should always be read before the high byte. the error counters are reset with the rising edge of the corresponding bits in the dec register. 1 = every second the error counter is latched and then automatically reset. the latched error counter state should be read within the next second. reading the error counter during updating should be avoided (do not access an error counter within 1 s after the one-second interrupt occurs). ssd0 select system data rate 0 fmr1.ssd0 and sic1.ssd1 define the data rate on the system highway. programming is done with ssd1/ssd0 in the following table. 00 = 2.048 mbit/s 01 = 4.096 mbit/s 10 = 8.192 mbit/s 11 = 16.384 mbit/s xais transmit ais towards remote end sends ais on ports xl1, xl2, xoid towards the remote end. the outgoing data stream which can be looped back through the local loop to the system interface is not affected. falc ? 56 pef 2256 h/e e1 registers user?s manual 242 ds1.1, 2003-10-23 hardware description framer mode register 2 (read/write) value after reset: 00 h rfs(1:0) receive framing select 00 = doubleframe format 01 = doubleframe format 10 = crc4 multiframe format 11 = crc4 multiframe format with modified crc4 multiframe alignment algorithm (interworking according to itu-t g.706 annex b). setting of fmr3.extiw changes the reaction after the 400-ms time-out. rtm receive transparent mode setting this bit disconnects control of the internal elastic store from the receiver. the elastic store is now in a ?free running? mode without any possibility to actualize the time slot assignment to a new frame position in case of resynchronization of the receiver. this function can be used together with the ?disable ais to system interface? feature (fmr2.dais) to realize undisturbed transparent reception. this bit should be enabled in case of unframed data reception mode. dais disable ais to system interface 0 = ais is automatically inserted into the data stream to rdo if falc ? 56 is in asynchronous state. 1 = automatic ais insertion is disabled. furthermore, ais insertion can be initiated by programming bit fmr2.sais. sais send ais towards system interface sends ais on output rdo towards system interface. this function is not influenced by bit fmr2.dais. plb payload loop-back 0 = normal operation. payload loop is disabled. 1 = the payload loop-back loops the data stream from the receiver section back to transmitter section. looped data is output on pin rdo. data received on port xdi, xsig, sypx and xmfs is ignored. with xsp.tt0 = 1 time slot 0 is also looped back. if xsp.tt0 = 0 time slot 0 is generated internally. ais is sent 70 fmr2 rfs1 rfs0 rtm dais sais plb axra almf (1e) falc ? 56 pef 2256 h/e e1 registers user?s manual 243 ds1.1, 2003-10-23 hardware description immediately on port rdo by setting the fmr2.sais bit. it is recommended to write the actual value of xc1 into this register once again, because a write access to register xc1 sets the read/write pointer of the transmit elastic buffer into its optimal position to ensure a maximum wander compensation (the write operation forces a slip). axra automatic transmit remote alarm 0 = normal operation 1 = the remote alarm bit is set automatically in the outgoing data stream if the receiver is in asynchronous state (frs0.lfa bit is set). in synchronous state the remote alarm bit is reset. additionally in multiframe format fmr2.rfs1 = 1 and fmr3.extiw = 1 and the 400-ms time-out has elapsed, the remote alarm bit is active in the outgoing data stream. in multiframe synchronous state the outgoing remote alarm bit is cleared. almf automatic loss of multiframe 0 = normal operation 1 = the receiver searches a new basic- and multiframing if more than 914 crc errors have been detected in a time interval of one second. the internal 914 crc error counter is reset if the multiframe synchronization is found. incrementing the counter is only enabled in the multiframe synchronous state. channel loop-back (read/write) value after reset: 00 h eclb enable channel loop-back 0 = disables the channel loop-back. 1 = enables the channel loop-back selected by this register. cla(4:0) channel address for loop-back cla = 0 to 31 selects the channel. during looped back the contents of the assigned outgoing channel on ports xl1/xdop/xoid and xl2/xdon is equal to the idle channel code programmed at register idle. 70 loop eclb cla4 cla3 cla2 cla1 cla0 (1f) falc ? 56 pef 2256 h/e e1 registers user?s manual 244 ds1.1, 2003-10-23 hardware description transmit service word pulseframe (read/write) value after reset: 00 h xsis spare bit for international use first bit of the service word. only significant in doubleframe format. if not used, this bit should be fixed to "1". if one of the time slot 0 transparent modes is enabled (bit xsp.tt0, or tswm.tsis), bit xsw.xsis is ignored. xtm transmit transparent mode 0 = ports sypx /xmfs define the frame/multiframe begin on the transmit system highway. the transmitter is usually synchronized on this externally sourced frame boundary and generates the fas-bits according to this framing. any change of the transmit time slot assignment subsequently produces a change of the fas-bit positions. 1 = disconnects the control of the transmit system interface from the transmitter. the transmitter is now in a free running mode without any possibility to actualize the multiframe position. the framing (fas-bits) generated by the transmitter is not ?disturbed? (in case of changing the transmit time slot assignment) by the transmit system highway unless register xc1 is written. useful in loop-timed applications. for proper operation the transmit elastic buffer (2 frames, sic1.xbs(1:0) = 10) has to be enabled. xra transmit remote alarm 0 = normal operation. 1 = sends remote alarm towards remote end by setting bit 3 of the service word. if time slot 0 transparent mode is enabled by bit xsp.tt0 or tswm.tra bit is set, bit xsw.xra is ignored. xy(4:0) spare bits for national use (y-bits, s n -bits, s a -bits) these bits are inserted in the service word of every other pulseframe if s a -bit register access is disabled (fmr1.ensa = 0). if not used, they should be fixed to ?1?. if one of the time slot 0 transparent modes is enabled (bit xsp.tt0 or tswm.tsa(8:4)), bits xsw.xy(4:0) are ignored. 70 xsw xsis xtm xra xy0 xy1 xy2 xy3 xy4 (20) falc ? 56 pef 2256 h/e e1 registers user?s manual 245 ds1.1, 2003-10-23 hardware description transmit spare bits (read/write) value after reset: 00 h casen channel associated signaling enable 0 = normal operation. 1 = a one in this bit position causes the transmitter to send the cas information stored in the xs(16:1) registers or serial cas data in the corresponding time slots. tt0 time slot 0 transparent mode 0 = normal operation. 1 = all information for time slot 0 on port xdi is inserted in the outgoing pulseframe. all internal information of the falc ? 56 (framing, crc, s a /s i -bit signaling, remote alarm) is ignored. this function is mainly useful for system test applications (test loops). priority sequence of transparent modes: xsp.tto > tswm. ebp e-bit polarity 0 = in the basic- and multiframe asynchronous state the e-bit is cleared. 1 = in the basic- and multiframe asynchronous state the e-bit is set. if automatic transmission of submultiframe status is enabled by setting bit xsp.axs and the receiver has lost synchronization, the e-bit with the programmed polarity is inserted automatically in s i -bit position of every outgoing crc multiframe (under the condition that time slot 0 transparent mode and transparent s i bit in service word are both disabled). axs automatic transmission of submultiframe status only applicable to crc multiframe. 0 = normal operation. 1 = information of submultiframe status bits rsp.si1 and rsp.si2 are inserted automatically in s i -bit positions of the outgoing crc multiframe (rsp.si1 s i -bit of frame 13; rsp.si2 s i -bit of frame 15). contents of xsp.xs13 and xsp.xs15 is 70 xsp casen tt0 ebp axs xsif xs13 xs15 (21) falc ? 56 pef 2256 h/e e1 registers user?s manual 246 ds1.1, 2003-10-23 hardware description ignored. if one of the time slot 0 transparent modes xsp.tt0 or tswm.tsis is enabled, bit xsp.axs has no function. xsif transmit spare bit for international use (fas word) first bit in the fas word. only significant in doubleframe format. if not used, this bit should be fixed to "1". if one of the time slot 0 transparent modes is enabled (bits xsp.tt0, or tswm.tsif), bit xsp.xsif is ignored. xs13 transmit spare bit (frame 13, crc-multiframe) first bit in the service word of frame 13 for international use. only significant in crc-multiframe format. if not used, this bit should be fixed to "1". the information of xsp.xs13 is shifted into internal transmission buffer with beginning of the next following transmitted crc multiframe. if automatic transmission of submultiframe status is enabled by bit xsp.axs, or, if one of the time slot 0 transparent modes xsp.tt0 or tswm.tsis is enabled, bit xsp.xs13 is ignored. xs15 transmit spare bit (frame 15, crc-multiframe) first bit in the service word of frame 15 for international use. only significant in crc-multiframe format. if not used, this bit should be fixed to "1". the information of xsp.xs15 is shifted into the internal transmission buffer with beginning of the next following transmitted crc multiframe. if automatic transmission of submultiframe status is enabled by bit xsp.axs, or, if one of the time slot 0 transparent modes xsp.tt0 or tswm.tsif is enabled, bit xsp.xs15 is ignored. transmit control 0 (read/write) value after reset: 00 h sa(8:4)e s a -bit signaling enable 0 = standard operation. 1 = setting this bit makes it possible to send/receive a lapd protocol in any combination of the s a -bit positions in the outgoing/incoming data stream. the on chip signaling controller has to be configured in the hdlc/lapd mode. in transmit 70 xc0 sa8e sa7e sa6e sa5e sa4e xco10 xco9 xco8 (22) falc ? 56 pef 2256 h/e e1 registers user?s manual 247 ds1.1, 2003-10-23 hardware description direction together with these bits the tswm.tsa(8:4) bits must be set to enable transmission to the remote end transparently through the falc ? 56. xco(10:8) transmit offset initial value loaded into the transmit bit counter at the trigger edge of sclkx when the synchronous pulse on port sypx /xmfs is active refer to register xc1. transmit control 1 (read/write) value after reset: 9c h a write access to this address resets the transmit elastic buffer to its basic starting position. therefore, updating the value should only be done when the falc ? 56 is initialized or when the buffer should be centered. as a consequence a transmit slip will occur. xco(7:0) transmit offset calculation of delay time t (sclkx cycles) depends on the value x of the ?transmit offset? register xc(1:0): 0 t 4: x = 4 - t 5 t maximum delay: x = 256 sc/sd - t + 4) with maximum delay = (256 sc/sd) -1 with sc = system clock defined by sic1.ssc(1:0) with sd = 2.048 mhz delay time t = time between beginning of time slot 0 (bit 0, channel phase 0) at xdi/xsig and the initial edge of sclkx after sypx /xmfs goes active. see page 114 for further description. 70 xc1 xco7 xco0 (23) falc ? 56 pef 2256 h/e e1 registers user?s manual 248 ds1.1, 2003-10-23 hardware description receive control 0 (read/write) value after reset: 00 h swd service word condition disable 0 = standard operation. three or four consecutive incorrect service words (depending on bit rc0.asy4) causes loss of synchronization. 1 = errors in service words have no influence when in synchronous state. however, they are used for the resynchronization procedure. asy4 select loss of sync condition 0 = standard operation. three consecutive incorrect fas words or three consecutive incorrect service words causes loss of synchronization. 1 = four consecutive incorrect fas words or four consecutive incorrect service words causes loss of synchronization. the service word condition is disabled by bit rc0.swd. crci automatic crc4 bit inversion if set, all crc bits of one outgoing submultiframe are inverted in case a crc error is flagged for the previous received submultiframe. this function is logically ored with rc0.xcrci. xcrci transmit crc4 bit inversion if set, the crc bits in the outgoing data stream are inverted before transmission. this function is logically ored with rc0.crci. rdis receive data input sense digital interface, dual-rail: 0 = inputs rdip/rdin are active low 1 = inputs rdip/rdin are active high digital interface, cmi: 0 = input roid is active high 1 = input roid is active low 70 rc0 swd asy4 crci xcrci rdis rco10 rco9 rco8 (24) falc ? 56 pef 2256 h/e e1 registers user?s manual 249 ds1.1, 2003-10-23 hardware description rco(10:8) receive offset/receive frame marker offset depending on the rp(a to d) pin function different offsets can be programmed. the sypr and the rfm pin function cannot be selected in parallel. receive offset (pc(4:1).rpc(2:0) = 000) initial value loaded into the receive bit counter at the trigger edge of sclkr when the synchronous pulse on port sypr is active. calculation of delay time t (sclkr cycles) depends on the value x of the receive offset register rc(1:0). for programing refer to register rc1. receive frame marker offset (pc(4:1).rpc(2:0) = 001 b ) offset programming of the receive frame marker which is output on port sypr . the receive frame marker can be activated during any bit position of the current frame. calculation of the value x of the receive offset register rc(1:0) depends on the bit position which should be marked and sclkr. refer to register rc1. receive control 1 (read/write) value after reset: 9c h rco(7:0) receive offset/receive frame marker offset depending on the rp(a to d) pin function different offsets can be programmed. the sypr and the rfm pin function cannot be selected in parallel. receive offset (pc(4:1).rpc(2:0) = 000) initial value loaded into the receive bit counter at the trigger edge of sclkr when the synchronous pulse on port sypr is active. calculation of delay time t (sclkr cycles) depends on the value x of the receive offset register rc(1:0): 0 t 4: x = 4 - t 5 t maximum delay:x = 2052 - t with maximum delay = (256 sc/sd) -1 with sc = system clock defined by sic1.ssc(1:0) with sd = system data rate 70 rc1 rco7 rco0 (25) falc ? 56 pef 2256 h/e e1 registers user?s manual 250 ds1.1, 2003-10-23 hardware description delay time t = time between beginning of time slot 0 at rdo and the initial edge of sclkr after sypr goes active. see page 109 for further description. receive frame marker offset (pc(4:1).rpc(2:0) = 001 b ) offset programming of the receive frame marker which is output on multifunction port rfm. the receive frame marker can be activated during any bit position of the entire frame and depends on the selected system clock rate. calculation of the value x of the receive offset register rc(1:0) depends on the bit position which should be marked at marker position mp: 0 mp 2045:x = mp + 2 2046 mp 2047: x = mp - 2046 e.g: 2.048 mhz: mp = 0 to 255; up to 16.384 mhz: mp = 0 to 2047 falc ? 56 pef 2256 h/e e1 registers user?s manual 251 ds1.1, 2003-10-23 hardware description transmit pulse mask (read/write) value after reset: 7b h , 03 h , 40 h the transmit pulse shape which is defined in itu-t g.703 is output on pins xl1 and xl2. the level of the pulse shape can be programmed by registers xpm(2:0) to create a custom waveform. in order to get an optimized pulse shape for the external transformers each pulse shape is internally divided into four sub pulse shapes. in each sub pulse shape a programmed 5 bit value defines the level of the analog voltage on pins xl1/2. together four 5-bit values have to be programmed to form one complete transmit pulse shape. the four 5-bit values are sent in the following sequence: changing the lsb of each subpulse in registers xpm(2:0) changes the amplitude of the differential voltage on xl1/2 by approximately 90 mv. setting of lim2.eou causes the values of xp20...23 and xp30...33 to be negative. example: 120 ? interface and wired as shown in figure 54 on page 160 . programming values for xpm(2:0): 00 h , 03 h , 9c h 70 xpm0 xp12 xp11 xp10 xp04 xp03 xp02 xp01 xp00 (26) xpm1 xp30 xp24 xp23 xp22 xp21 xp20 xp14 xp13 (27) xpm2 0 xlt daxlt 0 xp34 xp33 xp32 xp31 (28) xp04 to 00: first pulse shape level xp14 to 10: second pulse shape level xp24 to 20: third pulse shape level xp34 to 30: fourth pulse shape level xp04 to 00: 1c h or 28 decimal xp14 to 10: 1c h or 28 decimal xp24 to 20: 00 h xp34 to 30: 00 h falc ? 56 pef 2256 h/e e1 registers user?s manual 252 ds1.1, 2003-10-23 hardware description xlt transmit line tristate 0 = normal operation 1 = transmit line xl1/xl2 or xdop/xdon are switched into high-impedance state. if this bit is set the transmit line monitor status information is frozen (default value after hardware reset). daxlt disable automatic tristating of xl1/2 0 = normal operation. if a short is detected on pins xl1/2 the transmit line monitor sets the xl1/2 outputs into a high-impedance state. 1 = if a short is detected on xl1/2 pins automatic setting these pins into a high-impedance (by the xl-monitor) state is disabled. transparent service word mask (read/write) value after reset: 00 h tswm(7:0) transparent service word mask tsis transparent s i -bit in service word 0 = the s i -bit is generated internally. 1 = the s i -bit in the service word is taken from port xdi and transparently passed through the falc ? 56 without any changes. the internal information of the falc ? 56 (register xsw) is ignored. tsif transparent s i -bit in fas word 0 = the s i -bit is generated internally. 1 = the s i -bit in the fas word is taken from port xdi and routed transparently through the falc ? 56 without any changes. the internal information of the falc ? 56 (register xsw) is ignored. tra transparent remote alarm 0 = the remote alarm bit is generated internally. 1 = the a-bit is taken from port xdi and routed transparently through the falc ? 56 without any changes. the internal information of the falc ? 56 (register xsw) is ignored. 70 tswm tsis tsif tra tsa4 tsa5 tsa6 tsa7 tsa8 (29) falc ? 56 pef 2256 h/e e1 registers user?s manual 253 ds1.1, 2003-10-23 hardware description tsa(8:4) transparent s a (8:4)-bit 0 = the s a (8:4)-bits are generated internally. 1 = the s a (8:4)-bits are taken from port xdi or from the internal signaling controller if enabled and transparently passed through the falc ? 56 without any changes. the internal information of the falc ? 56 (registers xsw and xsa(8:4)) is ignored. idle channel code register (read/write) value after reset: 00 h idl(7:0) idle channel code if channel loop-back is enabled by programming loop.eclb = 1, the contents of the assigned outgoing channel on ports xl1/xl2 or xdop/xdon is set equal to the idle channel code selected by this register. additionally, the specified pattern overwrites the contents of all channels selected by the idle channel registers icb(4:1). idl7 is transmitted first. 70 idle idl7 idl0 (2b) falc ? 56 pef 2256 h/e e1 registers user?s manual 254 ds1.1, 2003-10-23 hardware description transmit s a (8:4) register (read/write) value after reset: 00 h , 00 h , 00 h , 00 h , 00 h xsa(8:4) transmit s a -bit data the s a -bit register access is enabled by setting bit fmr1.ensa = 1. with the transmit multiframe begin an interrupt isr1.xmb is generated and the contents of these registers xsa(8:4) is copied into a shadow register. the contents is subsequently sent out in the service words of the next outgoing crc multiframe (or doubleframes) if none of the time slot 0 transparent modes is enabled. xs40 is sent out in bit position 4 in frame 1, xs47 in frame 15. the transmit multiframe begin interrupt xmb request that these registers should be serviced. if requests for new information are ignored, current contents is repeated. 70 xsa4 xs47 xs46 xs45 xs44 xs43 xs42 xs41 xs40 (2c) xsa5 xs57 xs56 xs55 xs54 xs53 xs52 xs51 xs50 (2d) xsa6 xs67 xs66 xs65 xs64 xs63 xs62 xs61 xs60 (2e) xsa7 xs77 xs76 xs75 xs74 xs73 xs72 xs71 xs70 (2f) xsa8 xs87 xs86 xs85 xs84 xs83 xs82 xs81 xs80 (30) falc ? 56 pef 2256 h/e e1 registers user?s manual 255 ds1.1, 2003-10-23 hardware description framer mode register 3 (read/write) value after reset: 00 h xld transmit llb down code 0 = normal operation. 1 = a one in this bit position causes the transmitter to replace normal transmit data with the llb down (deactivate) code continuously until this bit is reset. the llb down code is optionally overwritten by the time slot 0 depending on bit lcr1.fllb. xlu transmit llb up code 0 = normal operation. 1 = a one in this bit position causes the transmitter to replace normal transmit data with the llb up code continuously until this bit is reset. the llb up code is overwritten by the time slot 0 depending on bit lcr1.fllb. for proper operation bit fmr3.xld must be cleared. cmi select cmi precoding only valid if cmi code (fmr0.xc(1:0) = 01) is selected. this bit defines the cmi precoding and influences transmit and receive data. 0 = cmi with hdb3 precoding 1 = cmi without hdb3 precoding note: before local loop is selected, hdb3 precoding has to be disabled. sa6sy receive s a 6-access synchronous mode only valid if multiframe format (fmr2.rfs(1:0) = 1x) is selected. 0 = the detection of the predefined s a 6-bit pattern (refer to chapter s a 6-bit detection according to ets 300233) is done independently of the multiframe synchronous state. 1 = the detection of the s a 6-bit pattern is done synchronously to the multiframe. 70 fmr3 xld xlu cmi sa6sy extiw (31) falc ? 56 pef 2256 h/e e1 registers user?s manual 256 ds1.1, 2003-10-23 hardware description extiw extended crc4 to non-crc4 interworking only valid in multiframe format. this bit selects the reaction of the synchronizer after the 400-ms time-out has been elapsed and starts transmitting a remote alarm if fmr2.axra is set. 0 = the crc4 to non crc4 interworking is done as described in itu-t g. 706 annex b. 1 = the interworking is done according to itu-t g. 706 with the exception that the synchronizer still searches the multiframing even if the 400-ms timer is expired. switching into doubleframe format is disabled. if fmr2.axra is set the remote alarm bit is active in the outgoing data stream until the multiframe is found. idle channel register (read/write) value after reset: 00 h , 00 h , 00 h , 00 h ic(31:0) idle channel selection bits these bits define the channels (time slots) of the outgoing pcm frame to be altered. assignments: ic0 time slot 0 ic1 time slot 1 ... ic31 time slot 31 0 = normal operation. 1 = idle channel mode. the contents of the selected time slot is overwritten by the idle channel code defined by register idle. note: although time slot 0 can be selected by bit ic0, its contents is only altered if the transparent mode is selected (xsp.tt0). 70 icb1 ic0 ic1 ic2 ic3 ic4 ic5 ic6 ic7 (32) icb2 ic8 ic9 ic10 ic11 ic12 ic13 ic14 ic15 (33) icb3 ic16 ic17 ic18 ic19 ic20 ic21 ic22 ic23 (34) icb4 ic24 ic25 ic26 ic27 ic28 ic29 ic30 ic31 (35) falc ? 56 pef 2256 h/e e1 registers user?s manual 257 ds1.1, 2003-10-23 hardware description line interface mode 0 (read/write) value after reset: 00 h xfb transmit full bauded mode only applicable for dual-rail mode (bit lim1.drs = 1). 0 = output signals xdop/xdon are half bauded. 1 = output signals xdop/xdon are full bauded. note: if cmi coding is selected (fmr0.xc(1:0) = 01) this bit has to be cleared. xdos transmit data out sense 0 = output signals xdop/xdon are active low. output xoid is active high (normal operation). 1 = output signals xdop/xdon are active high. output xoid is active low. note: if cmi coding is selected (fmr0.xc(1:0) = 01) this bit has to be cleared. the transmit frame marker xfm is independent of this bit. rtrs receive termination resistor switch 0 = default operation, switch is open. 1 = an integrated internal resistor between rl1 and rl2 is switched in addition to the external line termination resistor to achieve 75 ? line impedance matching. for further details regarding resistance values see chapter 4.1.7 on page 66 . dcim digital clocking interface mode 0 = default e1 data operation. 1 = selects synchronization interface mode according to itu-t g.703, section 13. a 2.048-mhz receive clock signal must be applied on rl1/rl2. the transmit clock signal must be derived from the clock connected to sclkx (cmr1.dxss = 1). the recommended xpm programming values are: xpm0 = ef h , xpm1 = bd h , xpm2 = 07 h 70 lim0 xfb xdos rtrs dcim 1 rlm ll mas (36) falc ? 56 pef 2256 h/e e1 registers user?s manual 258 ds1.1, 2003-10-23 hardware description rlm receive line monitoring 0 = normal receiver mode 1 = receiver mode for receive line monitoring; the receiver sensitivity is increased to detect resistively attenuated signals of -20 db (short-haul mode only) ll local loop 0 = normal operation 1 = local loop active. the local loop-back mode disconnects the receive lines rl1/rl2 or rdip/rdin from the receiver. instead of the signals coming from the line the data provided by system interface are routed through the analog receiver back to the system interface. the unipolar bit stream is transmitted undisturbedly on the line. receiver and transmitter coding must be identical. operates in analog and digital line interface mode. in analog line interface mode data is transferred through the complete analog receiver. mas master mode 0 = slave mode 1 = master mode on. setting this bit the dco-r circuitry is frequency synchronized to the clock (2.048 mhz or 8 khz, see ipc.ssyf) supplied by sync. if this pin is connected to v ss or v dd (or left open and pulled up to v dd internally) the dco-r circuitry is centered and no receive jitter attenuation is performed (only if 2.048 mhz clock is selected by resetting bit ipc.ssyf). the generated clocks are stable. line interface mode 1 (read/write) value after reset: 00 h clos clear data in case of los 0 = normal receiver mode, receive data stream is transferred normally in long-haul mode 1 = in long-haul mode received data is cleared (driven to low level), as soon as los is detected 70 lim1 clos ril2 ril1 ril0 jatt rl drs (37) falc ? 56 pef 2256 h/e e1 registers user?s manual 259 ds1.1, 2003-10-23 hardware description ril(2:0) receive input threshold only valid if analog line interface is selected (lim1.drs = 0). ?no signal? is declared if the voltage between pins rl1 and rl2 drops below the limits programmed by bits ril(2:0) and the received data stream has no transition for a period defined in the pcd register. the threshold where ?no signal? is declared is programmable by the ril(2:0) bits. see dc characteristics for detail. jatt, rl remote loop transmit jitter attenuator 00 = normal operation. the remote loop transmit jitter attenuator is disabled. transmit data bypasses the remote loop jitter attenuator buffer. 01 = remote loop active without remote loop transmit jitter attenuator enabled. transmit data bypasses the remote loop jitter attenuator buffer. 10 = not defined 11 = remote loop and remote loop jitter attenuator active. received data from pins rl1/2 or rdip/n or roid is sent "jitter-free" on ports xl1/2 or xdop/n or xoid. the de-jittered clock is generated by the dco-x circuitry. note:jatt is only used to define the jitter attenuation during remote loop operation. jitter attenuation during normal operation is not affected. drs dual-rail select 0 = the ternary interface is selected. multifunction ports rl1/2 and xl1/2 become analog in/outputs. 1 = the digital dual-rail interface is selected. received data is latched on multifunction ports rdip/rdin while transmit data is output on pins xdop/xdon. falc ? 56 pef 2256 h/e e1 registers user?s manual 260 ds1.1, 2003-10-23 hardware description pulse count detection register (read/write) value after reset: 00 h pcd(7:0) pulse count detection a los alarm is detected if the incoming data stream has no transitions for a programmable number t consecutive pulse positions. the number t is programmable by the pcd register and can be calculated as follows: t=16 (n+1); with 0 n 255. the maximum time is: 256 16 488 ns = 2 ms. every detected pulse resets the internal pulse counter. the counter is clocked with the receive clock rclk. pulse count recovery (read/write) value after reset: 00 h pcr(7:0) pulse count recovery a los alarm is cleared if a pulse-density is detected in the received bit stream. the number of pulses m which must occur in the predefined pcd time interval is programmable by the pcr register and can be calculated as follows: m = n+1; with 0 n 255. the time interval starts with the first detected pulse transition. with every received pulse a counter is incremented and the actual counter is compared to the contents of pcr register. if the pulse number is higher or equal to the pcr value the los alarm is reset otherwise the alarm stays active. in this case the next detected pulse transition starts a new time interval. 70 pcd pcd7 pcd0 (38) 70 pcr pcr7 pcr0 (39) falc ? 56 pef 2256 h/e e1 registers user?s manual 261 ds1.1, 2003-10-23 hardware description line interface mode 2 (read/write) value after reset: 20 h slt(1:0) receive slicer threshold 00 = the receive slicer generates a mark (digital one) if the voltage at rl1/2 exceeds 55% of the peak amplitude. 01 = the receive slicer generates a mark (digital one) if the voltage at rl1/2 exceeds 67% of the peak amplitude (recommended in some t1/j1 applications). 10 = the receive slicer generates a mark (digital one) if the voltage at rl1/2 exceeds 50% of the peak amplitude (default, recommended in e1 mode). 11 = the receive slicer generates a mark (digital one) if the voltage at rl1/2 exceeds 45% of the peak amplitude. scf select corner frequency of dco-r setting this bit reduces the corner frequency of the dco-r circuit by the factor of ten to 0.2 hz. note: reducing the corner frequency of the dco-r circuitry increases the synchronization time before the frequencies are synchronized. note: lim2.scf is ignored, if cmr2.ecfar is set. elt enable loop-timed 0 = normal operation 1 = transmit clock is generated from the clock supplied by mclk which is synchronized to the extracted receive route clock. in this configuration the transmit elastic buffer has to be enabled. refer to register xsw.xtm. for correct operation of loop timed the remote loop (bit lim1.rl = 0) must be inactive and bit cmr1.dxss must be cleared. mpas multi-purpose analog switch this bit controls the analog switch between pins as1 and as2. 0 = switch is open. 1 = switch is closed. 70 lim2 0 0 slt1 slt0 scf elt mpas eou (3a) falc ? 56 pef 2256 h/e e1 registers user?s manual 262 ds1.1, 2003-10-23 hardware description eou e1 pulse mask undershoot this bit controls the transmit pulse template during the 2nd half of the pulse. if enabled, the values programmed in xp3 and xp4 are used to generate a pulse undershoot. this can be used to achieve faster slew rates. 0 = xp3/xp4 are used as positive values. 1 = xp3/xp4 are used as negative values. loop code register 1 (read/write) value after reset: 00 h eprm enable pseudo-random binary sequence monitor 0 = pseudo-random binary sequence (prbs) monitor is disabled. 1 = prbs is enabled. setting this bit enables incrementing the cec2 error counter with each detected prbs bit error. with any change of state of the prbs internal synchronization status an interrupt isr1.llbsc is generated. the current status of the prbs synchronizer is indicated by bit rsp.llbad. xprbs transmit pseudo-random binary sequence a one in this bit position enables transmission of a pseudo-random binary sequence to the remote end. depending on bit llbp the prbs is generated according to 2 15 -1 or 2 20 -1 with a maximum-14-zero restriction (itu-t o. 151). ldc(1:0) length deactivate (down) code these bits defines the length of the llb deactivate code which is programmable in register lcr2. 00 = length: 5 bit 01 = length: 6 bit, 2 bit, 3 bit 10 = length: 7 bit 11 = length: 8 bit, 2 bit, 4bit 70 lcr1 eprm xprbs ldc1 ldc0 lac1 lac0 fllb llbp (3b) falc ? 56 pef 2256 h/e e1 registers user?s manual 263 ds1.1, 2003-10-23 hardware description lac(1:0) length activate (up) code these bits defines the length of the llb activate code which is programmable in register lcr3. 00 = length: 5 bit 01 = length: 6 bit, 2 bit, 3 bit 10 = length: 7 bit 11 = length: 8 bit, 2 bit, 4 bit fllb framed line loop-back/invert prbs depending on bit lcr1.xprbs this bit enables different functions: lcr1.xprbs = 0: 0 = the line loop-back code is transmitted including framing bits. llb code overwrites the framing bits. 1 = the line loop-back code is transmitted in framed mode. llb code does not overwrite the framing bits. invert prbs lcr1.xprbs = 1: 0 = the generated prbs is transmitted not inverted. 1 = the prbs is transmitted inverted. llbp line loop-back pattern lcr1.xprbs = 0 0 = fixed line loop-back code according to ansi t1. 403. 1 = enable user-programmable line loop-back code by register lcr2/3. lcr1.xprbs = 1 or lcr1.eprm = 1 0= 2 15 -1 1= 2 20 -1 falc ? 56 pef 2256 h/e e1 registers user?s manual 264 ds1.1, 2003-10-23 hardware description loop code register 2 (read/write) value after reset: 00 h ldc(7:0) line loop-back deactivate code if enabled by bit fmr3.xld = 1 the llb deactivate code automatically repeats until the llb generator is stopped. transmit data is overwritten by the llb code. ldc0 is transmitted last. for correct operations bit lcr1.xprbs has to cleared. if lcr2 is changed while the previous deactivate code has been detected and is still received, bit rsp.llbdd will stay active until the incoming signal changes or a receiver reset is initiated (cmdr.rres = 1). loop code register 3 (read/write) value after reset: 00 h lac(7:0) line loop-back activate code if enabled by bit fmr3.xlu = 1 the llb activate code automatically repeats until the llb generator is stopped. transmit data is overwritten by the llb code. lac0 is transmitted last. for correct operations bit lcr1.xprbs has to cleared. if lcr3 is changed while the previous activate code has been detected and is still received, bit rsp.llbad will stay active until the incoming signal changes or a receiver reset is initiated (cmdr.rres = 1). 70 lcr2 ldc7 ldc0 (3c) 70 lcr3 lac7 lac0 (3d) falc ? 56 pef 2256 h/e e1 registers user?s manual 265 ds1.1, 2003-10-23 hardware description system interface control 1 (read/write) value after reset: 00 h ssc(1:0) select system clock sic1.ssc(1:0) define the clocking rate on the system highway. 00 = 2.048 mhz 01 = 4.096 mhz 10 = 8.192 mhz 11 = 16.384 mhz ssd1 select system data rate 1 sic1.ssd1 and fmr1.ssd0 define the data rate on the system highway. programming ssd1/ssd0 and corresponding data rate is shown below. 00 = 2.048 mbit/s 01 = 4.096 mbit/s 10 = 8.192 mbit/s 11 = 16.384 mbit/s rbs(1:0) receive buffer size 00 = buffer size: 2 frames 01 = buffer size: 1 frame 10 = buffer size: 96 bits 11 = bypass of receive elastic store bim bit interleaved mode 0 = byte interleaved mode 1 = bit interleaved mode xbs(1:0) transmit buffer size 00 = bypass of transmit elastic store 01 = buffer size: 1 frame 10 = buffer size: 2 frames 11 = buffer size: 96 bits 70 sic1 ssc1 ssd1 rbs1 rbs0 ssc0 bim xbs1 xbs0 (3e) falc ? 56 pef 2256 h/e e1 registers user?s manual 266 ds1.1, 2003-10-23 hardware description system interface control 2 (read/write) value after reset: 00 h ffs force freeze signaling setting this bit disables updating of the receive signaling buffer and current signaling information is frozen. after resetting this bit and receiving a complete superframe updating of the signaling buffer is started again. the freeze signaling status can also be automatically generated by detecting the loss-of-signal alarm or a loss of cas frame alignment or a receive slip (only if external register access on pin rsig is enabled). this automatic freeze signaling function is logically ored with this bit. the current internal freeze signaling status is output on pin rpa to rpd using pin function freeze which is selected by pc(4:1).rpc(2:0) = 110. additionally, this status is also available in register sis.sfs. ssf serial signaling format only applicable if pin function rsig/xsig and sic3.ttrf = 0 is selected. 0 = bits 1 to 4 in all time slots except time slots 0 and16 are cleared. 1 = bits 1 to 4 in all time slots except time slots 0 and16 are set high. crb center receive elastic buffer only applicable if the time slot assigner is disabled (pc(4:1).rpc(2:0) = 001 b ), no external or internal synchronous pulse receive is generated. a transition from low to high forces a receive slip and the read- pointer of the receive elastic buffer is centered. the delay through the buffer is set to one half of the current buffer size. it should be hold high for at least two 2.048 mhz periods before it is cleared. sics(2:0) system interface channel select only applicable if the system clock rate is greater than 2.048 mhz. received data is transmitted on pin rdo/rsig or received on xdi/xsig with the selected system data rate. if the data rate is greater than 2.048 mbit/s the data is output or sampled in half, a 70 sic2 ffs ssf crb sics2 sics1 sics0 (3f) falc ? 56 pef 2256 h/e e1 registers user?s manual 267 ds1.1, 2003-10-23 hardware description quarter or one eighth of the time slot. data is not repeated. the time while data is active during a 8 488 ns time slot is called a channel phase. rdo/rsig are cleared (driven to low level) while xdi/xsig are ignored for the remaining time of the 8 488 ns or for the remaining channel phases. the channel phases are selectable with these bits. 000 = data active in channel phase 1, valid if system data rate is 16/8/4 mbit/s 001 = data active in channel phase 2, valid if system data rate is 16/8/4 mbit/s 010 =data active in channel phase 3, valid if data rate is 16/8 mbit/s 011 = data active in channel phase 4, valid if data rate is 16/8 mbit/s 100 = data active in channel phase 5, valid if data rate is 16 mbit/s 101 = data active in channel phase 6, valid if data rate is 16 mbit/s 110 = data active in channel phase 7, valid if data rate is 16 mbit/s 111 = data active in channel phase 8, valid if data rate is 16 mbit/s system interface control 3 (read/write) value after reset: 00 h casmf cas multiframe begin marker 0 = the time slot 0 multiframe begin is asserted on pin rp(a to d)/pin function rmfb. 1 = the time slot 16 cas multiframe begin is asserted on pin rp(a to d)/pin function rmfb. rtri rdo/rsig tri-state mode 0 during incative channel phases, rdo and rsig are switched to low output level. 1 during incative channel phases, rdo and rsig are switched into tri-state mode. fsct sec/fsc tri-state mode 0 normal operation. 1 sec/fsc output is switched into tri-state mode. 70 sic3 casmf rtri fsct resx resr ttrf daf (40) falc ? 56 pef 2256 h/e e1 registers user?s manual 268 ds1.1, 2003-10-23 hardware description resx rising edge synchronous pulse transmit depending on this bit all transmit system interface data and marker are clocked or sampled with the selected active edge. cmr2.ixsc = 0: 0 latched with the first falling edge of the selected pcm highway clock. 1 latched with the first rising edge of the selected pcm highway clock. cmr2.ixsc = 1: the value of resx bit has no impact on the selected edge of the pcm highway clock but value of resr bit is used as resx. example: if resr = 0, the rising edge of pcm highway clock is the selected one for sampling data on xdi and vice versa. resr rising edge synchronous pulse receive depending on this bit all receive system interface data and marker are clocked with the selected active edge. 0 = latched with the first falling edge of the selected pcm highway clock. 1 = latched with the first rising edge of the selected pcm highway clock. note: if bit cmr2.irsp is set, the behavior of signal rfm (if used) is inverse (1 = falling edge, 0 = rising edge) ttrf ttr register function (fractional e1 access) setting this bit the function of the ttr(4:1) registers is changed. a one in each ttr register forces the xsigm marker high for the corresponding time slot and controls sampling of the time slots provided on pin xsig. xsig is selected by pc(4:1).xpc(3:0). daf disable automatic freeze 0 = signaling is automatically frozen if one of the following alarms occurred: loss-of-signal (frs0.los), loss of cas frame alignment (frs1.ts16lfa), or receive slips (isr3.rsp/n). 1 = automatic freezing of signaling data is disabled. updating of the signaling buffer is also done if one of the above described alarm conditions is active. however, updating of the signaling buffer is stopped if sic2.ffs is set. significant only if the serial signaling access is enabled. falc ? 56 pef 2256 h/e e1 registers user?s manual 269 ds1.1, 2003-10-23 hardware description clock mode register 1 (read/write) value after reset: 00 h rs(1:0) select rclk source these bits select the source of rclk. 00 = clock recovered from the line through the dpll drives rclk 01 = clock recovered from the line through the dpll drives rclk and in case of an active los alarm rclk pin is set high. 10 = clock recovered from the line is de-jittered by dco-r to drive a 2.048 mhz clock on rclk. 11 = clock recovered from the line is de-jittered by dco-r to drive a 8.192 mhz clock on rclk. dcs disable clock-switching in slave mode (lim0.mas = 0) the dco-r is synchronized on the recovered route clock. in case of loss-of-signal los the dco-r switches automatically to the clock sourced by port sync. setting this bit automatic switching from rclk to sync is disabled. stf select tclk frequency only applicable if the pin function tclk port xp(a to d) is selected by pc(4:1).xpc(3:0) = 0011 b . data on xl1/2 (xdop/n / xoid) are clocked with tclk. 0 = 2.048 mhz 1 = 8.192 mhz dxja disable internal transmit jitter attenuation setting this bit disables the transmit jitter attenuation. reading the data out of the transmit elastic buffer and transmitting on xl1/2 (xdop/n/xoid) is done with the clock provided on pin tclk. in transmit elastic buffer bypass mode the transmit clock is taken from sclkx, independent of this bit. 70 cmr1 rs1 rs0 dcs stf dxja dxss (44) falc ? 56 pef 2256 h/e e1 registers user?s manual 270 ds1.1, 2003-10-23 hardware description dxss dco-x synchronization clock source 0 = the dco-x circuitry synchronizes to the internal reference clock which is sourced by sclkx/r or rclk. since there are many reference clock opportunities the following internal prioritizing in descending order from left to right is realized: lim1.rl > cmr1.dxss > lim2.elt > current working clock of transmit system interface. if one of these bits is set the corresponding reference clock is taken. 1 = dco-x synchronizes to an external reference clock provided on pin xp(a to d) pin function tclk, if no remote loop is active. tclk is selected by pc(4:1).xpc(3:0) = 0011 b . clock mode register 2 (read/write) value after reset: 00 h ecfax enable corner frequency adjustment for dco-x 0 = corner frequency adjustment is disabled. 1 = corner frequency adjustment is enabled, values are programmed in cmr3.cfax (see page 274 ). note:dco-x must be enabled. ecfar enable corner frequency adjustment for dco-r 0 = corner frequency adjustment is disabled. 1 = corner frequency adjustment is enabled, values are programmed in cmr3.cfar (see page 274 ). lim2.scf is ignored. note:dco-r must be enabled. dcoxc dco-x center-frequency enable 0 = the center function of the dco-x circuitry is disabled. 1 = the center function of the dco-x circuitry is enabled. dco-x centers to 2.048 mhz related to the master clock reference (mclk), if reference clock (e.g. sclkx) is missing. 70 cmr2 ecfax ecfar dcoxc dcf irsp irsc ixsp ixsc (45) falc ? 56 pef 2256 h/e e1 registers user?s manual 271 ds1.1, 2003-10-23 hardware description dcf dco-r center- frequency disabled 0 = the dco-r circuitry is frequency centered - in master mode if no 2.048 mhz reference clock on pin sync is provided or - in slave mode if a loss-of-signal occurs in combination with no 2.048 mhz clock on pin sync or - a gapped clock is provided on pin rclki and this clock is inactive or stopped. 1 = the center function of the dco-r circuitry is disabled. the generated clock (dco-r) is frequency frozen in that moment when no clock is available on pin sync or pin rclki. the dco-r circuitry starts synchronization as soon as a clock appears on pins sync or rclki. irsp internal receive system frame sync pulse 0 = the frame sync pulse for the receive system interface is sourced by sypr (if sypr is applied). if sypr is not applied, the frame sync pulse is derived from rdo output signal internally free running). the use of irsp = 0 is recommended. 1 = the frame sync pulse for the receive system interface is internally sourced by the dco-r circuitry. this internally generated frame sync signal can be output (active low) on multifunction ports rp(a to d) (rpc(2:0) = 001 b ). note: this is the only exception where the use of rfm and sypr is allowed at the same time. because only one set of offset registers (rc1/0) is available, programming is done by using the sypr calculation formula in the same way as for the external sypr pulse. bit irsc must be set for correct operation. irsc internal receive system clock 0 = the working clock for the receive system interface is sourced by sclkr or in receive elastic buffer bypass mode from the corresponding extracted receive clock rclk. 1 = the working clock for the receive system interface is sourced internally by dco-r or in bypass mode by the extracted receive clock. sclkr is ignored. falc ? 56 pef 2256 h/e e1 registers user?s manual 272 ds1.1, 2003-10-23 hardware description ixsp internal transmit system frame sync pulse 0 = the frame sync pulse for the transmit system interface is sourced by sypx . 1 = the frame sync pulse for the transmit system interface is internally sourced by the dco-r circuitry. additionally, the external xmfs signal defines the transmit multiframe begin. xmfs is enabled or disabled by the multifunction port configuration. for correct operation bits cmr2.ixsc/irsc must be set. sypx is ignored. ixsc internal transmit system clock 0 = the working clock for the transmit system interface is sourced by sclkx. 1 = the working clock for the transmit system interface is sourced internally by the working clock of the receive system interface. sclkx is ignored. falc ? 56 pef 2256 h/e e1 registers user?s manual 273 ds1.1, 2003-10-23 hardware description global configuration register (read/write) value after reset: 00 h vis masked interrupts visible 0 = masked interrupt status bits are not visible in registers isr(5:0). 1 = masked interrupt status bits are visible in isr(5:0), but they are not visible in register gis. sci status change interrupt 0 = interrupts are generated either on activation or deactivation of the internal interrupt source. 1 = the following interrupts are activated both on activation and deactivation of the internal interrupt source: isr2.los, isr2.ais, isr3.lmfa16 ses select external second timer 0 = internal second timer selected 1 = external second timer selected ecmc error counter mode cofa 0 = the s a 6-bit error indications are accumulated in the error counter cec3l/h. 1 = a change of frame or multiframe alignment cofa is detected since the last resynchronization. the events are accumulated in the error counter cec3l.(1:0). multiframe periods received in the asynchronous state are accumulated in the error counter cec3l.7-2. an overflow of each counter is disabled. pd power down switches between power-up and power-down mode. 0= power up 1= power down all outputs are driven inactive; multifunction ports are driven high by the weak internal pullup device. 70 gcr vis sci ses ecmc pd (46) falc ? 56 pef 2256 h/e e1 registers user?s manual 274 ds1.1, 2003-10-23 hardware description errored second mask (read/write) value after reset: ff h esm errored second mask this register functions as an additional mask register for the interrupt status bit errored second (isr3.es). a "1" in a bit position of esm deactivates the related second interrupt. clock mode register 3 (read/write) value after reset: 00 h disable error counter (write) value after reset: 00 h drbd disable receive buffer delay this bit has to be set before reading the register rbd. it is reset automatically if rbd has been read. dcec3 disable crc error counter 3 dcec2 disable crc error counter 2 dcec1 disable crc error counter 70 esm lfa fer cer ais los cve slip ebe (47) 70 cmr3 cfax(3:0) cfar(3:0) (48) table 62 dco-r and dco-x corner frequency programing (e1) cfax(3:0) dco-x corner frequency [hz] cfar(3:0) dco-r corner frequency [hz] 7 h 0.2 7 0.2 4 h 2.0 4 2.0 70 dec drbd dcec3 dcec2 dcec1 debc dcvc dfec (60) falc ? 56 pef 2256 h/e e1 registers user?s manual 275 ds1.1, 2003-10-23 hardware description debc disable errored block counter dcvc disable code violation counter dfec disable framing error counter these bits are only valid if fmr1.ecm is cleared. they have to be set before reading the error counters. they are reset automatically if the corresponding error counter high byte has been read. with the rising edge of these bits the error counters are latched and then cleared. note: error counters and receive buffer delay can be read 1 s after setting the according bit in bit dec. falc ? 56 pef 2256 h/e e1 registers user?s manual 276 ds1.1, 2003-10-23 hardware description transmit cas register (write) value after reset: not defined transmit cas register (16:1) the transmit cas register access is enabled by setting bit xsp.casen = 1. each register except xs1 contains the cas bits for two time slots. with the transmit multiframe begin isr1.xmb the contents of these regist ers is copied into a shadow register. the contents is sent out subsequently in the time slots 16 of the outgoing data stream. note: if isr1.xmb is not used and the write access to these registers is done exact in the moment when this interrupt is generated, data is lost. xs1.7 is sent out first and xs16.0 is sent last. the transmit multiframe begin interrupt (xmb) requests that these registers should be serviced. if requests for new information are ignored, current contents is repeated. xs1 has to be programmed with the multiframe pattern. this pattern should always stay low otherwise the remote end loses its synchronization. with setting the y-bit a remote alarm is transmitted to the far end. the x bits (spare bits) should be set if they are not used. table 63 transmit cas registers (e1) 70 xs1 0000xyxx (70) xs2 a1 b1 c1 d1 a16 b16 c16 d16 (71) xs3 a2 b2 c2 d2 a17 b17 c17 d17 (72) xs4 a3 b3 c3 d3 a18 b18 c18 d18 (73) xs5 a4 b4 c4 d4 a19 b19 c19 d19 (74) xs6 a5 b5 c5 d5 a20 b20 c20 d20 (75) xs7 a6 b6 c6 d6 a21 b21 c21 d21 (76) xs8 a7 b7 c7 d7 a22 b22 c22 d22 (77) xs9 a8 b8 c8 d8 a23 b23 c23 d23 (78) xs10 a9 b9 c9 d9 a24 b24 c24 d24 (79) xs11 a10 b10 c10 d10 a25 b25 c25 d25 (7a) xs12 a11 b11 c11 d11 a26 b26 c26 d26 (7b) xs13 a12 b12 c12 d12 a27 b27 c27 d27 (7c) xs14 a13 b13 c13 d13 a28 b28 c28 d28 (7d) xs15 a14 b14 c14 d14 a29 b29 c29 d29 (7e) xs16 a15 b15 c15 d15 a30 b30 c30 d30 (7f) falc ? 56 pef 2256 h/e e1 registers user?s manual 277 ds1.1, 2003-10-23 hardware description if access to these registers is done without control of the interrupt isr1.xmb the registers should be written twice to avoid an internal data transfer error. note: a software reset (cmdr.xres) resets these registers. port configuration 1 to 4 (read/write) value after reset: 00 h rpc(3:0) receive multifunction port configuration the multifunction ports rp(a to d) are bidirectional. after reset these ports are configured as inputs. with the selection of the pin function the in/output configuration is also achieved. the input function sypr may only be selected once, it must not be selected twice or more. register pc1 configures port rpa, while pc2 port rpb, pc3 port rpc and pc4 port rpd. 0000 = sypr : synchronous pulse receive (input) together with register rc(1:0) sypr defines the frame begin on the receive system interface. because of the offset programming the sypr and the rfm pin function cannot be selected in parallel. 0001 = rfm: receive frame marker (output) cmr2.irsp = 0 and gpc1.srfm = 0: the receive frame marker is active high for one 2.048 mhz period during any bit position of the current frame. programming of the bit position is done by using registers rc(1:0). the internal time slot assigner is disabled. the rfm offset calculation formula has to be used. cmr2.irsp = 0 and gpc1.srfm = 1: the receive frame marker is active high for one system period as programmed by sic1.ssc during any bit position of the current frame. programming of the bit position is done by using registers rc(1:0). the internal time slot assigner is disabled. the rfm offset calculation formula has to be used. 70 pc1 rpc13 rpc12 rpc11 rpc10 xpc13 xpc12 xpc11 xpc10 (80) pc2 rpc23 rpc22 rpc21 rpc20 xpc23 xpc22 xpc21 xpc20 (81) pc3 rpc33 rpc32 rpc31 rpc30 xpc33 xpc32 xpc31 xpc30 (82) pc4 rpc43 rpc42 rpc41 rpc40 xpc43 xpc42 xpc41 xpc40 (83) falc ? 56 pef 2256 h/e e1 registers user?s manual 278 ds1.1, 2003-10-23 hardware description cmr2.irsp = 1: internally generated frame synchronization pulse sourced by the dco-r circuitry. the pulse is active low for one 2.048 mhz period. 0010 = rmfb: receive multiframe begin (output) marks the beginning of every received multiframe or optionally the begin of every cas multiframe begin (active high). 0011 = rsigm: receive signaling marker (output) marks the time slots which are defined by register rtr(4:1) of every frame on port rdo. 0100 = rsig: receive signaling data (output) the received cas multiframe is transmitted on this pin. time slot on rsig correlates directly to the time slot assignment on rdo. 0101 = dlr: data link bit receive (output) marks the s a -bits within the data stream on rdo. 0110 = freeze: freeze signaling (output) the freeze signaling status is active high by detecting a loss-of-signal alarm, or a loss of cas frame alignment or a receive slip (positive or negative). it stays high for at least one complete multiframe after the alarm disappears. setting sic2.ffs enforces a high on pin freeze. 0111 = rfsp : receive frame synchronous pulse (output) marks the frame begin in the receivers synchronous state. this marker is active low for 488 ns with a frequency of 8 khz. 1001 = gpi: general purpose input 1010 = gpoh: general purpose output high 1011 = gpol: general purpose output low 1100 = los: loss of signal output (status of frs0.los) xpc(3:0) transmit multifunction port configuration the multifunction ports xp(a to d) are bidirectional. after reset these ports are configured as inputs. with the selection of the pin function the in/output configuration is also achieved. each of the four different input functions (sypx , xmfs, xsig, tclk) may only be selected once. no input function must be selected twice or more. sypx and xmfs should not be selected in parallel. register pc1 configures port xpa, while pc2 port xpb, pc3 port xpc and pc4 port xpd. falc ? 56 pef 2256 h/e e1 registers user?s manual 279 ds1.1, 2003-10-23 hardware description 0000 = sypx : synchronous pulse transmit (input) together with register xc(1:0) sypx defines the frame begin on the transmit system interface ports xdi and xsig. 0001 = xmfs: transmit multiframe synchronization (input) together with register xc(1:0) xmfs defines the frame and multiframe begin on the transmit system interface ports xdi and xsig. depending on pc5.cxmfs the signal on xmfs is active high or low. 0010 = xsig: transmit signaling data (input) input for transmit signaling data received from the signaling highway. optionally sampling of xsig data is controlled by the active high xsigm marker. 0011 = tclk: transmit clock (input) a 2.048/8.192 mhz clock has to be sourced by the system if the internal generated transmit clock (dco-x) is not used. optionally this input is used as a synchronization clock for the dco-x circuitry with a frequency of 2.048 mhz. 0100 = xmfb: transmit multiframe begin (output) marks the beginning of every transmit multiframe. 0101 = xsigm: transmit signaling marker (output) marks the time slots which are defined by register ttr(4:1) of every frame on port xdi. 0110 = dlx: data link bit transmit (output) marks the s a -bits within the data stream on xdi. 0111 = xclk: transmit line clock (output) frequency: 2.048 mhz 1000 = xlt: transmit line tristate (input) with a high level on this port the transmit lines xl1/2 or xdop/n are set directly into tristate. this pin function is logically ored with register xpm2.xlt. 1001 = gpi: general purpose input 1010 = gpoh: general purpose output high 1011 = gpol: general purpose output low falc ? 56 pef 2256 h/e e1 registers user?s manual 280 ds1.1, 2003-10-23 hardware description port configuration 5 (read/write) value after reset: 00 h phdsx phase decoder switch for dco-x 0 = switch phase decoder divider by 1/3 1 = switch phase decoder divider by 1/6 (slower adaption speed) phdsr phase decoder switch for dco-r 0 = switch phase decoder divider by 1/3 1 = switch phase decoder divider by 1/6 (slower adaption speed) cclk2 configure clk2 port 0 = clk2 is input 1 = clk2 is output (only, if dco-x is active) cclk1 configure clk1 port 0 = clk1 is input 1 = clk1 is output (only, if dco-r is active) cxmfs configure xmfs port 0 = port xmfs is active low. 1 = port xmfs is active high. csrp configure sclkr port 0 = sclkr: input 1 = sclkr: output crp configure rclk port 0 = rclk: input 1 = rclk: output 70 pc5 phdsx phdsr cclk2 cclk1 cxmfs 0 csrp crp (84) falc ? 56 pef 2256 h/e e1 registers user?s manual 281 ds1.1, 2003-10-23 hardware description global port configuration 1 (read/write) value after reset: 00 h csfp(1:0) configure sec/fsc port the fsc pulse is generated if the dco-r circuitry of the selected channel is active (cmr2.irsc = 1 or cmr1.rs(1:0) = 10 or 11). sec/fsc can be switched into tristate mode by setting sic3.fsct. 00 = sec: input, active high 01 = sec: output, active high 10 = fsc: output, active high 11 = fsc: output, active low srfm set rfm according to system clock 0 = outgoing rfm on pin rpx is active high for 488 ns independent of the programmed system clock frequency. 1 = outgoing rfm on pin rpx is active high for one system clock period as programmed by sic.ssc. note:only valid if corresponding pcx.rpc = 0001 b and cmr2.irsp = 0. 70 gpc1 csfp1 csfp0 srfm (85) falc ? 56 pef 2256 h/e e1 registers user?s manual 282 ds1.1, 2003-10-23 hardware description port configuration 6 (read/write) value after reset: 00 h sxcl(1:0) select transmit clock frequency on port clk2 port clk2 is the de-jittered dco-x clock at a frequency of 00 = 2.048 mhz 01 = 4.096 mhz 10 = 8.192 mhz 11 = 16.384 mhz note: if dco-x is not used, no clock is output on pin clk2 (sic1.xbs(1:0)=00 and cmr1.dxja=1; buffer bypass and no jitter attenuation) scl(2:0) select system clock frequency on port clk1 port clk1 is the de-jittered dco-r clock at a frequency of 000 = 8 khz 001 = 2.048 mhz 010 = 4.096 mhz 011 = 8.192 mhz 100 = 16.384 mhz 101 to 111 = not defined note: if dco-r is not active, no clock is output on pin clk1 (sic1.rbs(1:0)=11 and cmr1.rs1=0). 70 pc6 sxcl1 sxcl0 scl2 scl1 scl0 (86) falc ? 56 pef 2256 h/e e1 registers user?s manual 283 ds1.1, 2003-10-23 hardware description command register 2 (write) value after reset: 00 h rsuc reset signaling unit counter after setting this bit the ss7 signaling unit counter and error counter are reset.the bit is cleared automatically after execution. note: the maximum time between writing to the cmdr2 register and the execution of the command takes 2.5 periods of the current system data rate. therefore, if the cpu operates with a very high clock rate in comparison with the falc ? 56's clock, it is recommended that bit sis.cec should be checked before writing to the cmdr2 register to avoid any loss of commands. command register 3 (write) value after reset: 00 h rmc2 receive message complete - hdlc channel 2 confirmation from cpu to falc ? that the current frame or data block has been fetched following an rpf2 or rme2 interrupt, thus the occupied space in the rfifo2 can be released. xrep2 transmission repeat - hdlc channel 2 if xrep2 is set together with xtf2 (write 24h to cmdr3), the falc ? repeatedly transmits the contents of the xfifo2 (1 to 32 bytes) without hdlc framing fully transparently, i.e. without flag, crc. the cyclic transmission is stopped with an sres2 command or by resetting xrep2. xhf2 transmit hdlc frame - hdlc channel 2 after having written up to 32 bytes to the xfifo2, this command initiates the transmission of a hdlc frame. cmdr2 rsuc (x87) 70 cmdr3 rmc2 xrep2 xhf2 xtf2 xme2 sres2 (88) falc ? 56 pef 2256 h/e e1 registers user?s manual 284 ds1.1, 2003-10-23 hardware description xtf2 transmit transparent frame - hdlc channel 2 initiates the transmission of a transparent frame without hdlc framing. xme2 transmit message end - hdlc channel 2 indicates that the data block written last to the xfifo2 completes the current frame. the falc ? can terminate the transmission operation properly by appending the crc and the closing flag sequence to the data. sres2 signaling transmitter reset - hdlc channel 2 the transmitter of the signaling controller is reset. xfifo2 is cleared of any data and an abort sequence (seven 1s) followed by interframe time fill is transmitted. in response to sres2 an xpr2 interrupt is generated. this command can be used by the cpu to abort a frame currently in transmission. command register 4 (write) value after reset: 00 h rmc3 receive message complete - hdlc channel 3 confirmation from cpu to falc ? that the current frame or data block has been fetched following an rpf3 or rme3 interrupt, thus the occupied space in the rfifo3 can be released. xrep3 transmission repeat - hdlc channel 3 if xrep3 is set together with xtf3 (write 24h to cmdr4), the falc ? repeatedly transmits the contents of the xfifo3 (1 to 32 bytes) without hdlc framing fully transparently, i.e. without flag, crc. the cyclic transmission is stopped with an sres3 command or by resetting xrep3. xhf3 transmit hdlc frame - hdlc channel 3 after having written up to 32 bytes to the xfifo3, this command initiates the transmission of a hdlc frame. 70 cmdr4 rmc3 xrep3 xhf3 xtf3 xme3 sres3 (89) falc ? 56 pef 2256 h/e e1 registers user?s manual 285 ds1.1, 2003-10-23 hardware description xtf3 transmit transparent frame - hdlc channel 3 initiates the transmission of a transparent frame without hdlc framing. xme3 transmit message end - hdlc channel 3 indicates that the data block written last to the xfifo3 completes the current frame. the falc ? can terminate the transmission operation properly by appending the crc and the closing flag sequence to the data. sres3 signaling transmitter reset - hdlc channel 3 the transmitter of the signaling controller is reset. xfifo3 is cleared of any data and an abort sequence (seven 1s) followed by interframe time fill is transmitted. in response to sres3 an xpr3 interrupt is generated. this command can be used by the cpu to abort a frame currently in transmission. common configuration register 3 (read/write) value after reset: 00 h radd2 receive address pushed to rfifo2 if this bit is set, the received hdlc channel 2 address information (1 or 2 bytes, depending on the address mode selected via mode2.mds02) is pushed to rfifo2. this function is applicable in non-auto mode and transparent mode 1. rcrc2 receive crc on/off - hdlc channel 2 only applicable in non-auto mode. if this bit is set, the received crc checksum is written to rfifo2 (crc-itu-t: 2 bytes). the checksum, consisting of the 2 last bytes in the received frame, is followed in the rfifo2 by the status information byte (contents of register rsis2). the received crc checksum will additionally be checked for correctness. if non-auto mode is selected, the limits for ?valid frame? check are modified. 70 ccr3 radd2 rcrc2 xcrc2 itf2 xmfa2 rft12 rft02 (8b) falc ? 56 pef 2256 h/e e1 registers user?s manual 286 ds1.1, 2003-10-23 hardware description xcrc2 transmit crc on/off - hdlc channel 2 if this bit is set, the crc checksum will not be generated internally. it has to be written as the last two bytes in the transmit fifo (xfifo2). the transmitted frame is closed automatically with a closing flag. itf2 interframe time fill - hdlc channel 2 determines the idle (= no data to be sent) state of the transmit data coming from the signaling controller. 0 = continuous logical "1" is output 1 = continuous flag sequences are output ("01111110" bit patterns) xmfa2 transmit multiframe aligned - hdlc channel 2 determines the synchronization between the framer and the corresponding signaling controller. 0 = the contents of the xfifo2 is transmitted without multiframe alignment. 1 = the contents of the xfifo2 is transmitted multiframe aligned. rft12, rft02 rfifo2 threshold level - hdlc channel 2 the size of the accessible part of rfifo2 can be determined by programming these bits. the number of valid bytes after an rpf interrupt is given in the following table: the value of rft(1:0)2 can be changed dynamically if reception is not running or after the current data block has been read, but before the command cmdr3.rmc2 is issued (interrupt controlled data transfer). rft12 rft02 size of accessible part of rfifo2 0 0 1 1 0 1 0 1 32 bytes (default value) 16 bytes 4 bytes 2 bytes falc ? 56 pef 2256 h/e e1 registers user?s manual 287 ds1.1, 2003-10-23 hardware description common configuration register 4 (read/write) value after reset: 00 h radd3 receive address pushed to rfifo3 if this bit is set, the received hdlc channel 3 address information (1 or 2 bytes, depending on the address mode selected via mode3.mds03) is pushed to rfifo3. this function is applicable in non-auto mode and transparent mode 1. rcrc3 receive crc on/off - hdlc channel 3 only applicable in non-auto mode. if this bit is set, the received crc checksum is written to rfifo3 (crc-itu-t: 2 bytes). the checksum, consisting of the 2 last bytes in the received frame, is followed in the rfifo3 by the status information byte (contents of register rsis3). the received crc checksum will additionally be checked for correctness. if non-auto mode is selected, the limits for ?valid frame? check are modified. xcrc3 transmit crc on/off - hdlc channel 3 if this bit is set, the crc checksum will not be generated internally. it has to be written as the last two bytes in the transmit fifo (xfifo3). the transmitted frame is closed automatically with a closing flag. itf3 interframe time fill - hdlc channel 3 determines the idle (= no data to be sent) state of the transmit data coming from the signaling controller. 0 = continuous logical "1" is output 1 = continuous flag sequences are output ("01111110" bit patterns) xmfa3 transmit multiframe aligned - hdlc channel 3 determines the synchronization between the framer and the corresponding signaling controller. 0 = the contents of the xfifo3 is transmitted without multiframe alignment. 1 = the contents of the xfifo3 is transmitted multiframe aligned. 70 ccr4 radd3 rcrc3 xcrc3 itf3 xmfa3 rft13 rft03 (8c) falc ? 56 pef 2256 h/e e1 registers user?s manual 288 ds1.1, 2003-10-23 hardware description rft13, rft03 rfifo3 threshold level - hdlc channel 3 the size of the accessible part of rfifo3 can be determined by programming these bits. the number of valid bytes after an rpf interrupt is given in the following table: the value of rft13/03 can be changed dynamically if reception is not running or after the current data block has been read, but before the command cmdr4.rmc3 is issued (interrupt controlled data transfer). common configuration register 5 (read/write) value after reset: 00 h note:these bits are only valid, if ss7 mode of hdlc channel 1 is selected. csf2 compare status field - mode 2 0 = compare disabled, if consecutive fisus are equal, only the first is stored and all following are ignored. 1 = compare enabled, if consecutive fisus are equal, the first two are stored and all following are ignored (according to itu-t q.703). suet signaling unit error threshold defines the number of signaling units received in error that will cause an error rate high indication (isr1.suex). 0 = threshold 64 errored signaling units 1 = threshold 32 errored signaling units csf compare status field if the status fields of consecutive lssus are equal, only the first is stored and every following is ignored. rft13 rft03 size of accessible part of rfifo3 0 0 1 1 0 1 0 1 32 bytes (default value) 16 bytes 4 bytes 2 bytes 70 ccr5 csf2 suet csf afx (x8d) falc ? 56 pef 2256 h/e e1 registers user?s manual 289 ds1.1, 2003-10-23 hardware description 0 = compare disabled. 1 = compare enabled. afx automatic fisu transmission after the contents of the transmit fifo (xfifo) has been transmitted completely, fisus are transmitted automatically. these fisus contain the fsn and bso of the last transmitted signaling unit. 0 = automatic fisu transmission disabled. 1 = automatic fisu transmission enabled. mode register 2 (read/write) value after reset: 00 h mds2(2:0) mode select - hdlc channel 2 the operating mode of the hdlc controller is selected. 000 = reserved 001 = reserved 010 = one-byte address comparison mode (ral1, 2) 011 = two-byte address comparison mode (rah1, 2 and ral1, 2) 100 = no address comparison 101 = one-byte address comparison mode (rah1, 2) 110 = reserved 111 = no hdlc framing mode 1 hrac2 receiver active - hdlc channel 2 switches the hdlc receiver to operational or inoperational state. 0 = receiver inactive 1 = receiver active div2 data inversion - hdlc channel 2 setting this bit will invert the internal generated hdlc data stream. 0 = normal operation, hdlc data stream not inverted 1 = hdlc data stream inverted 70 mode2 mds22 mds21 mds20 hrac2 div2 hdlci2 (8e) falc ? 56 pef 2256 h/e e1 registers user?s manual 290 ds1.1, 2003-10-23 hardware description hdlci2 inverse hdlc operation - hdlc channel 2 setting this bit selects the hdlc channel 2 operation mode. 0 = normal operation, hdlc attached to line side 1 = inverse operation, hdlc attached to system side. hdlc data is received on xdi and transmitted on rdo. mode register 3 (read/write) value after reset: 00 h mds3(2:0) mode select - hdlc channel 3 the operating mode of the hdlc controller is selected. 000 = reserved 001 = reserved 010 = one-byte address comparison mode (ral1, 2) 011 = two-byte address comparison mode (rah1, 2 and ral1, 2) 100 = no address comparison 101 = one-byte address comparison mode (rah1, 2) 110 = reserved 111 = no hdlc framing mode 1 hrac3 receiver active - hdlc channel 3 switches the hdlc receiver to operational or inoperational state. 0 = receiver inactive 1 = receiver active div3 data inversion - hdlc channel 3 setting this bit will invert the internal generated hdlc data stream. 0 = normal operation, hdlc data stream not inverted 1 = hdlc data stream inverted 70 mode3 mds32 mds31 mds30 hrac3 div3 hdlci3 (8f) falc ? 56 pef 2256 h/e e1 registers user?s manual 291 ds1.1, 2003-10-23 hardware description hdlci3 inverse hdlc operation - hdlc channel 3 setting this bit selects the hdlc channel 3 operation mode. 0 = normal operation, hdlc attached to line side 1 = inverse operation, hdlc attached to system side. hdlc data is received on xdi and transmitted on rdo. global clock mode register 1 (read/write) value after reset: 00 h see table 64 for programming. global clock mode register 2 (read/write) value after reset: 00 h see table 64 for programming. global clock mode register 3 (read/write) value after reset: 00 h see table 64 for programming. global clock mode register 4 (read/write) value after reset: 00 h see table 64 for programming. 70 gcm1 gcm1(7:0) (92) 70 gcm2 gcm2(7:0 (93) 70 gcm3 gcm3(7:0) (94) 70 gcm4 gcm4(7:0) (95) falc ? 56 pef 2256 h/e e1 registers user?s manual 292 ds1.1, 2003-10-23 hardware description global clock mode register 5 (read/write) value after reset: 00 h see table 64 for programming. global clock mode register 6 (read/write) value after reset: 00 h see table 64 for programming. global clock mode register 7 (read/write) value after reset: 00 h see table 64 for programming. global clock mode register 8 (read/write) value after reset: 00 h see table 64 for programming. 70 gcm5 gcm5(7:0) (96) 70 gcm6 gcm6(7:0) (97) 70 gcm7 gcm7(7:0) (98) 70 gcm8 gcm8(7:0) (99) falc ? 56 pef 2256 h/e e1 registers user?s manual 293 ds1.1, 2003-10-23 hardware description transmit fifo 2 (write) value after reset: 00 h xf(15:0) transmit fifo for hdlc channel 2 the function is equivalent to xfifo. transmit fifo 3 (write) value after reset: 00 h xf(15:0) transmit fifo for hdlc channel 3 the function is equivalent to xfifo. table 64 gcmx register programming line frequency [mhz] mclk [mhz] register settings (xx = don?t care) gcm1 gcm2 gcm3 gcm4 gcm5 gcm6 gcm7 gcm8 2.048 2.048 00 h 00 h xx xx 00 h 3f h 80 h xx 8.192 00 h 00 h xx xx 02 h 30 h a0 h xx 10 a2 h 0f h xx xx 03 h 34 h 90 h xx 12.352 5a h 0a h xx xx 04 h 35 h 90 h xx 16.384 49 h 02 h xx xx 06 h 38 h a0 h xx 19.44 70 h 01 h xx xx 04 h 21 h 90 h xx 70 xfifo2 xf7 xf0 (x9c) xfifo2 xf15 xf8 (x9d) 70 xfifo3 xf7 xf0 (x9e) xfifo3 xf15 xf8 (x9f) falc ? 56 pef 2256 h/e e1 registers user?s manual 294 ds1.1, 2003-10-23 hardware description time slot even/odd select (read/write) value after reset: 00 h hdlc protocol data can be sent in even, odd or both frames of a multiframe. even frames are frame number 2, 4,and so on, odd frames are frame number 1, 3, and so on. the selection refers to receive and transmit direction as well. each multiframe starts with an odd frame and ends with an even frame. by default all frames are used for hdlc reception and transmission. note: the different hdlc channels have to be configured to use different time slots, bit positions or frames. eo1(1:0) even/odd frame selection hdlc channel 1 channel 1 hdlc protocol data can be sent in even, odd or both frames of a multiframe. 00 = even and odd frames 01 = odd frames only 10 = even frames only 11 = undefined eo2(1:0) even/odd frame selection hdlc channel 2 channel 2 hdlc protocol data can be sent in even, odd or both frames of a multiframe. 00 = even and odd frames 01 = odd frames only 10 = even frames only 11 = undefined eo3(1:0) even/odd frame selection hdlc channel 3 channel 3 hdlc protocol data can be sent in even, odd or both frames of a multiframe. 00 = even and odd frames 01 = odd frames only 10 = even frames only 11 = undefined 70 tseo eo31 eo30 eo21 eo20 eo11 eo10 (a0) falc ? 56 pef 2256 h/e e1 registers user?s manual 295 ds1.1, 2003-10-23 hardware description time slot bit select 1 (read/write) value after reset: ff h tsb1(7:0) time slot bit selection - hdlc channel 1 only bits selected by this register are used for hdlc channel 1 in selected time slots. time slot selection is done by setting the appropriate bits in registers ttr(4:1) and rtr(4:1) independently for receive and transmit direction. bit selection is common to receive and transmit direction. by default all bit positions within the selected time slot(s) are enabled. 0 = bit position x in selected time slot(s) is not used for hdlc channel 1 reception and transmission. 1 = bit position x in selected time slot(s) is used for hdlc channel 1 reception and transmission. time slot bit select 2 (read/write) value after reset: ff h tsb2(7:0) time slot bit selection - hdlc channel 2 only bits selected by this register are used for hdlc channel 2 in selected time slots. time slot selection is done by setting the appropriate bits in register tss2. bit selection is common to receive and transmit direction. by default all bit positions within the selected time slot are enabled. 0 = bit position x in selected time slot(s) is not used for hdlc channel 2 reception and transmission. 1 = bit position x in selected time slot(s) is used for hdlc channel 2 reception and transmission. 70 tsbs1 tsb17 tsb16 tsb15 tsb14 tsb13 tsb12 tsb11 tsb10 (a1) 70 tsbs2 tsb27 tsb26 tsb25 tsb24 tsb23 tsb22 tsb21 tsb20 (a2) falc ? 56 pef 2256 h/e e1 registers user?s manual 296 ds1.1, 2003-10-23 hardware description time slot bit select 3 (read/write) value after reset: ff h tsb3(7:0) time slot bit selection - hdlc channel 3 only bits selected by this register are used for hdlc channel 3 in selected time slots. time slot selection is done by setting the appropriate bits in register tss3. bit selection is common to receive and transmit direction. by default all bit positions within the selected time slot are enabled. 0 = bit position x in selected time slot(s) is not used for hdlc channel 3 reception and transmission. 1 = bit position x in selected time slot(s) is used for hdlc channel 3 reception and transmission. time slot select 2 (read/write) value after reset: 00 h tss2(4:0) time slot selection code - hdlc channel 2 defines the time slot used by hdlc channel 2. 00000 =no time slot selected 00001 =time slot 1 ... 11111 =time slot 31 note:different hdlc channels must use different time slots. 70 tsbs3 tsb37 tsb36 tsb35 tsb34 tsb33 tsb32 tsb31 tsb30 a3) 70 tss2 tss24 tss23 tss22 tss21 tss20 (a4) falc ? 56 pef 2256 h/e e1 registers user?s manual 297 ds1.1, 2003-10-23 hardware description time slot select 3 (read/write) value after reset: 00 h ts3(4:0) time slot selection code - hdlc channel 3 defines the time slot used by hdlc channel 3. 00000 =no time slot selected 00001 =time slot 1 ... 11111 =time slot 31 note:different hdlc channels must use different time slots. test pattern control register 0 (read/write) value after reset: 00 h fra framed/unframed selection 0 = prbs is generated/monitored unframed. framing information is overwritten by the generator. 1 = prbs is generated/monitored framed. time slot 0 is not overwritten by the generator and not observed by the monitor. 70 tss3 tss34 tss33 tss32 tss31 tss30 (a5) 70 tpc0 fra (a8) falc ? 56 pef 2256 h/e e1 registers user?s manual 298 ds1.1, 2003-10-23 hardware description global line control register 1 (read/write) value after reset: 00 h rlrrw receive line ram read/write select 0 = read access 1 = write access ers receive line ram access enable 0 = ram access disabled 1 = ram access enabled attention: as long as ers = 1 is selected, only ram access is possible and no register can be read or written to. a read acces to address f8h clears ers and enables normal operation. 70 glc1 0 0 0 0 0 0 ramrw ramen (af) falc ? 56 pef 2256 h/e e1 registers user?s manual 299 ds1.1, 2003-10-23 hardware description 9.3 e1 status register addresses table 65 e1 status register address arrangement address register type comment page 00 rfifo r receive fifo 301 01 rfifo r receive fifo 301 49 rbd r receive buffer delay 302 4a vstr r version status register 303 4b res r receive equalizer status 303 4c frs0 r framer receive status 0 304 4d frs1 r framer receive status 1 307 4e rsw r receive service word 308 4f rsp r receive spare bits 309 50 fecl r framing error counter low 311 51 fech r framing error counter high 311 52 cvcl r code violation counter low 312 53 cvch r code violation counter high 312 54 cec1l r crc error counter 1 low 313 55 cec1h r crc error counter 1 high 313 56 ebcl r e-bit error counter low 314 57 ebch r e-bit error counter high 314 58 cec2l r crc error counter 2 low 315 59 cec2h r crc error counter 2 high 315 5a cec3l r crc error counter 3 low 316 5b cec3h r crc error counter 3 high 316 5c rsa4 r receive s a 4-bit register 317 5d rsa5 r receive s a 5-bit register 317 5e rsa6 r receive s a 6-bit register 317 5f rsa7 r receive s a 7-bit register 317 60 rsa8 r receive s a 8-bit register 317 61 rsa6s r receive s a 6-bit status register 318 62 rsp1 r receive signaling pointer 1 319 63 rsp2 r receive signaling pointer 2 319 falc ? 56 pef 2256 h/e e1 registers user?s manual 300 ds1.1, 2003-10-23 hardware description 64 sis r signaling status register 320 65 rsis r receive signaling status register 321 66 rbcl r receive byte control low 323 67 rbch r receive byte control high 323 68 isr0 r interrupt status register 0 323 69 isr1 r interrupt status register 1 325 6a isr2 r interrupt status register 2 327 6b isr3 r interrupt status register 3 329 6c isr4 r interrupt status register 4 330 6d isr5 r interrupt status register 5 332 6e gis r global interrupt status 335 70 rs1 r receive cas register 1 336 71 rs2 r receive cas register 2 336 72 rs3 r receive cas register 3 336 73 rs4 r receive cas register 4 336 74 rs5 r receive cas register 5 336 75 rs6 r receive cas register 6 336 76 rs7 r receive cas register 7 336 77 rs8 r receive cas register 8 336 78 rs9 r receive cas register 9 336 79 rs10 r receive cas register 10 336 7a rs11 r receive cas register 11 336 7b rs12 r receive cas register 12 336 7c rs13 r receive cas register 13 336 7d rs14 r receive cas register 14 336 7e rs15 r receive cas register 15 336 7f rs16 r receive cas register 16 336 90 rbc2 r receive byte count register 2 337 91 rbc3 r receive byte count register 3 337 9a sis3 r signaling status register 3 340 table 65 e1 status register address arrangement (cont?d) address register type comment page falc ? 56 pef 2256 h/e e1 registers user?s manual 301 ds1.1, 2003-10-23 hardware description 9.4 detailed description of e1 status registers receive fifo - hdlc channel 1 (read) reading data from rfifo of hdlc channel 1 can be done in an 8-bit (byte) or 16-bit (word) access depending on the selected bus interface mode. the lsb is received first from the serial interface. the size of the accessible part of rfifo is determined by programming the bits ccr1.rft(1:0) (rfifo threshold level). it can be reduced from 32 bytes (reset value) down to 2 bytes (four values: 32, 16, 4, 2 bytes). data transfer up to 32 bytes/16 words of received data can be read from the rfifo following an rpf or an rme interrupt. rpf interrupt: a fixed number of bytes/words to be read (32, 16, 4, 2 bytes). the message is not yet complete. rme interrupt: the message is completely received. the number of valid bytes is determined by reading the rbcl, rbch registers. rfifo is released by issuing the rmc ( r eceive m essage c omplete) command. 9b rsis3 r receive signaling status register 3 341 9c rfifo2 r receive fifo 2 343 9d rfifo2 r receive fifo 2 343 9e rfifo3 r receive fifo 3 343 9f rfifo3 r receive fifo 3 343 a9 sis2 r signaling status register 2 337 aa rsis2 r receive signaling status register 2 339 ab mfpi r multifunction port input status 343 70 rfifo rf7 rf0 (00) rfifo rf15 rf8 (01) table 65 e1 status register address arrangement (cont?d) address register type comment page falc ? 56 pef 2256 h/e e1 registers user?s manual 302 ds1.1, 2003-10-23 hardware description receive buffer delay (read) rbd(5:0) receive elastic buffer delay these bits informs the user about the current delay (in time slots) through the receive elastic buffer. the delay is updated every 512 or 256 bits (sic1.rbs(1:0)). before reading this register the user has to set bit dec.drbd in order to halt the current value of this register. after reading rbd updating of this register is enabled. not valid if the receive buffer is bypassed. 000000 = delay < 1 time slot ... 111111 = delay > 63 time slots 70 rbd rbd5 rbd4 rbd3 rbd2 rbd1 rbd0 (49) falc ? 56 pef 2256 h/e e1 registers user?s manual 303 ds1.1, 2003-10-23 hardware description version status register (read) vn(7:0) version number of chip 00 h =version 1.2 10 h =version 2.1 receive equalizer status (read) ev(1:0) equalizer status valid these bits informs the user about the current state of the receive equalization network. 00 = equalizer status not valid, still adapting 01 = equalizer status valid 10 = equalizer status not valid 11 = equalizer status valid but high noise floor res(4:0) receive equalizer status the current line attenuation status in steps of about 1.7 db are displayed in these bits. only valid if bits ev(1:0) = 01. accuracy: 2 digits, based on temperature influence and noise amplitude variations. 00000 = minimum attenuation: 0 db ... 11001 = maximum attenuation: -43 db 70 vstr vn7 vn0 (4a) 70 res ev1 ev0 res4 res3 res2 res1 res0 (4b) falc ? 56 pef 2256 h/e e1 registers user?s manual 304 ds1.1, 2003-10-23 hardware description framer receive status register 0 (read) los loss-of-signal detection : this bit is set when the incoming signal has ?no transitions? (analog interface) or logical zeros (digital interface) in a time interval of t consecutive pulses, where t is programmable by register pcd. total account of consecutive pulses: 16 < t < 4096. analog interface: the receive signal level where ?no transition? is declared is defined by the programmed value of lim1.ril(2:0). recovery : analog interface: the bit is reset in short-haul mode when the incoming signal has transitions with signal levels greater than the programmed receive input level (lim1.ril(2:0)) for at least m pulse periods defined by register pcr in the pcd time interval. in long-haul mode additionally bit res.6 must be set for at least 250sec. digital interface: the bit is reset when the incoming data stream contains at least m ones defined by register pcr in the pcd time interval. with the rising edge of this bit an interrupt status bit (isr2.los) is set. the bit is also set during alarm simulation and reset, if fmr0.sim is cleared and no alarm condition exists. ais alarm indication signal the function of this bit is determined by fmr0.alm. fmr0.alm = 0: this bit is set when two or less zeros in the received bit stream are detected in a time interval of 250 s and the falc ? 56 is in asynchronous state (frs0.lfa = 1). the bit is reset when no alarm condition is detected (according to etsi standard). fmr0.alm = 1: this bit is set when the incoming signal has two or less zeros in each of two consecutive double frame period (512 bits). this bit is cleared when each of two consecutive doubleframe periods contain three or more zeros or when the frame alignment signal fas has been found. (itu-t g.775) the bit is also set during alarm simulation and reset if fmr0.sim is cleared and no alarm condition exists. with the rising edge of this bit an interrupt status bit (isr2.ais) is set. 70 frs0 los ais lfa rra nmf lmfa (4c) falc ? 56 pef 2256 h/e e1 registers user?s manual 305 ds1.1, 2003-10-23 hardware description lfa loss of frame alignment this bit is set after detecting 3 or 4 consecutive incorrect fas words or 3 or 4 consecutive incorrect service words (can be disabled). with the rising edge of this bit an interrupt status bit (isr2.lfa) is set. the specification of the loss of synchronization conditions is done by bits rc0.swd and rc0.asy4. after loss of synchronization, the frame aligner resynchronizes automatically. the following conditions have to be detected to regain synchronous state: ? the presence of the correct fas word in frame n. ? the presence of the correct service word (bit 2 = 1) in frame n+1. ? for a second time the presence of a correct fas word in frame n+2. the bit is cleared when synchronization has been regained (directly after the second correct fas word of the procedure described above has been received). if the crc-multiframe structure is enabled by setting bit fmr2.rfs1, multiframe alignment is assumed to be lost if pulseframe synchronization has been lost. the resynchronization procedure for multiframe alignment starts after the bit frs0.lfa has been cleared. multiframe alignment has been regained if two consecutive crc-multiframes have been received without a framing error (refer to frs0.lmfa). the bit is set during alarm simulation and reset if fmr0.sim is cleared and no alarm condition exists. if bit frs0.lfa is cleared a loss of frame alignment recovery interrupt status isr2.far is generated. rra receive remote alarm set if bit 3 of the received service word is set. an alarm interrupt status isr2.ra can be generated if the alarm condition is detected. frs0.rra is cleared if no alarm is detected. at the same time a remote alarm recovery interrupt status isr2.rar is generated. the bit rsw.rra has the same function. both status and interrupt status bits are set during alarm simulation. falc ? 56 pef 2256 h/e e1 registers user?s manual 306 ds1.1, 2003-10-23 hardware description nmf no multiframe alignment found this bit is only valid if the crc4 interworking is selected (fmr2.rfs(1:0) = 11). set if the multiframe pattern is not detected in a time interval of 400 ms after the framer has reached the doubleframe synchronous state. the receiver is then automatically switched to doubleframe format. this bit is reset if the basic framing has been lost. lmfa loss of multiframe alignment not used in doubleframe format (fmr2.rfs1 = 0). in this case lmfa is set. in crc-multiframe mode (fmr2.rfs1 = 1), this bit is set ? if force resynchronization is initiated by setting bit fmr0.frs, or ? if multiframe force resynchronization is initiated by setting bit fmr1.mfcs, or ? if pulseframe alignment has been lost (frs0.lfa). it is reset if two crc-multiframes have been received at an interval of n 2 ms (n = 1, 2, 3 and so forth) without a framing error. if bit frs0.lmfa is cleared a loss of multiframe alignment recovery interrupt status isr2.mfar is generated. falc ? 56 pef 2256 h/e e1 registers user?s manual 307 ds1.1, 2003-10-23 hardware description framer receive status register 1 (read) exzd excessive zeros detected significant only, if excessive zero detection has been enabled (fmr0.exze = 1). set after detection of more than 3 (hdb3 code) or 15 (ami code) contiguous zeros in the received data stream. this bit is cleared on read. ts16ra receive time slot 16 remote alarm this bit contains the actual information of the received remote alarm bit rs1.2 in time slot 16. setting and resetting of this bit causes an interrupt status change isr3.ra16. ts16los receive time slot 16 loss-of-signal this bit is set if the incoming ts16 data stream contains always zeros for at least 16 contiguously received time slots. a one in a time slot 16 resets this bit. ts16ais receive time slot 16 alarm indication signal the detection of the alarm indication signal in time slot 16 is according to itu-t g.775. this bit is set if the incoming ts16 contains less than 4 zeros in each of two consecutive ts16 multiframe periods. this bit is cleared if two consecutive received cas multiframe periods contains more than 3 zeros or the multiframe pattern was found in each of them. this bit is cleared if ts0 synchronization is lost. ts16lfa receive time slot 16 loss of multiframe alignment 0 = the cas controller is in synchronous state after frame alignment is accomplished. 1 = this bit is set if the framing pattern "0000" in 2 consecutive cas multiframes were not found or in all ts16 of the preceding multiframe all bits were reset. an interrupt isr3.lmfa16 is generated. 70 frs1 exzd ts16ra ts16los ts16ais ts16lfa xls xlo (4d) falc ? 56 pef 2256 h/e e1 registers user?s manual 308 ds1.1, 2003-10-23 hardware description xls transmit line short significant only if the ternary line interface is selected by lim1.drs = 0. 0 = normal operation. no short is detected. 1 = the xl1 and xl2 are shortened for at least 3 pulses. as a reaction of the short the pins xl1 and xl2 are automatically forced into a high-impedance state if bit xpm2.daxlt is reset. after 128 consecutive pulse periods the outputs xl1/2 are activated again and the internal transmit current limiter is checked. if a short between xl1/2 is still further active the outputs xl1/2 are in high-impedance state again. when the short disappears pins xl1/2 are activated automatically and this bit is reset. with any change of this bit an interrupt isr1.xlsc is generated. in case of xpm2.xlt is set this bit is frozen. xlo transmit line open 0 = normal operation 1 = this bit is set if at least 32 consecutive zeros were sent on pins xl1/xl2 or xdop/xdon. this bit is reset with the first transmitted pulse. with the rising edge of this bit an interrupt isr1.xlsc is set. in case of xpm2.xlt is set this bit is frozen. receive service word pulseframe (read) rsi receive spare bit for international use first bit of the received service word. it is fixed to one if crc-multiframe mode is enabled. rra receive remote alarm equivalent to bit frs0.rra. ry(4:0) receive spare bits for national use (y-bits, s n -bits, s a -bits) 70 rsw rsi rra ry0 ry1 ry2 ry3 ry4 (4e) falc ? 56 pef 2256 h/e e1 registers user?s manual 309 ds1.1, 2003-10-23 hardware description receive spare bits/additional status (read) si(2:1) submultiframe error indication 1, 2 not valid if doubleframe format is enabled. in this case, both bits are set. when using crc-multiframe format these bits are set to 0 = if multiframe alignment has been lost, or if the last multiframe has been received with crc error(s). si1 flags a crc error in last submultiframe 1, si2 flags a crc error in last submultiframe 2. 1 = if at multiframe synchronous state last assigned submultiframe has been received without a crc error. both flags are updated with the beginning of every received crc multiframe. if automatic transmission of submultiframe status is enabled by setting bit xsp.axs, above status information is inserted automatically in s i -bit position of every outgoing crc multiframe (under the condition that time slot 0 transparent modes are both disabled): si1 s i -bit of frame 13, si2 s i -bit of frame 15. llbdd line loop-back deactivation signal detected this bit is set in case of the llb deactivate signal is detected and then received over a period of more than 25 ms with a bit error rate less than 10 -2 . the bit remains set as long as the bit error rate does not exceed 10 -2 . if framing is aligned, the time slot 0 is not taken into account for the error rate calculation. any change of this bit causes an llbsc interrupt. llbad line loop-back activation signal detected depending on bit lcr1.eprm the source of this status bit changed. lcr1.eprm = 0: this bit is set in case of the llb activate signal is detected and then received over a period of more than 25 ms with a bit error rate less than 10 -2 . the bit remains set as long as the bit error rate does not exceed 10 -2 . 70 rsp si1 si2 llbdd llbad rsif rs13 rs15 (4f) falc ? 56 pef 2256 h/e e1 registers user?s manual 310 ds1.1, 2003-10-23 hardware description if framing is aligned, the time slot 0 is not taken into account for the error rate calculation. any change of this bit causes an llbsc interrupt. prbs status lcr1.eprm = 1: the current status of the prbs synchronizer is indicated in this bit. it is set high if the synchronous state is reached even in the presence of a bit error rate of 10 -1 . a data stream containing all zeros or all ones with/without framing bits is also a valid pseudo-random binary sequence. rsif receive spare bit for international use (fas word) first bit in fas-word. used only in doubleframe format, otherwise fixed to "1". rs13 receive spare bit (frame 13, crc multiframe) first bit in service word of frame 13. significant only in crc-multiframe format, otherwise fixed to "0". this bit is updated with beginning of every received crc multiframe. rs15 receive spare bit (frame 15, crc multiframe) first bit in service word of frame 15. significant only in crc-multiframe format, otherwise fixed to "0". this bit is updated with beginning of every received crc multiframe. falc ? 56 pef 2256 h/e e1 registers user?s manual 311 ds1.1, 2003-10-23 hardware description framing error counter (read) fe(15:0) framing errors this 16-bit counter is incremented when a fas word has been received with an error. framing errors are counted during basic frame synchronous state only (but even if multiframe synchronous state is not reached yet). during alarm simulation, the counter is incremented every 250 s up to its saturation. the error counter does not roll over. clearing and updating the counter is done according to bit fmr1.ecm. if this bit is reset the error counter is permanently updated in the buffer. for correct read access of the error counter bit dec.dfec has to be set. with the rising edge of this bit updating the buffer is stopped and the error counter is reset. bit dec.dfec is reset automatically with reading the error counter high byte. if fmr1.ecm is set every second (interrupt isr3.sec) the error counter is latched and then automatically reset. the latched error counter state should be read within the next second. 70 fecl fe7 fe0 (50) 70 fech fe15 fe8 (51) falc ? 56 pef 2256 h/e e1 registers user?s manual 312 ds1.1, 2003-10-23 hardware description code violation counter (read) cv(15:0) code violations no function if nrz code has been enabled. if the hdb3 or the cmi code with hdb3-precoding is selected, the 16-bit counter is incremented when violations of the hdb3 code are detected. the error detection mode is determined by programming the bit fmr0.extd. if simple ami coding is enabled (fmr0.rc0/1 = 10) all bipolar violations are counted. the error counter does not roll over. during alarm simulation, the counter is incremented every four bits received up to its saturation. clearing and updating the counter is done according to bit fmr1.ecm. if this bit is reset the error counter is permanently updated in the buffer. for correct read access of the error counter bit dec.dcvc has to be set. with the rising edge of this bit updating the buffer is stopped and the error counter is reset. bit dec.dcvc is reset automatically with reading the error counter high byte. if fmr1.ecm is set every second (interrupt isr3.sec) the error counter is latched and then automatically reset. the latched error counter state should be read within the next second. 70 cvcl cv7 cv0 (52) 70 cvch cv15 cv8 (53) falc ? 56 pef 2256 h/e e1 registers user?s manual 313 ds1.1, 2003-10-23 hardware description crc error counter 1 (read) cr(15:0) crc errors no function if doubleframe format is selected. in crc-multiframe mode, the 16-bit counter is incremented when a crc-submultiframe has been received with a crc error. crc errors are not counted during asynchronous state. the error counter does not roll over. during alarm simulation, the counter is incremented once per submultiframe up to its saturation. clearing and updating the counter is done according to bit fmr1.ecm. if this bit is reset the error counter is permanently updated in the buffer. for correct read access of the error counter bit dec.dcec1 has to be set. with the rising edge of this bit updating the buffer is stopped and the error counter is reset. bit dec.dcec1 is reset automatically with reading the error counter high byte. if fmr1.ecm is set every second (interrupt isr3.sec) the error counter is latched and then automatically reset. the latched error counter state should be read within the next second. 70 cec1l cr7 cr0 (54) 70 cec1h cr15 cr8 (55) falc ? 56 pef 2256 h/e e1 registers user?s manual 314 ds1.1, 2003-10-23 hardware description e-bit error counter (read) eb(15:0) e-bit errors if doubleframe format is selected, febeh/l has no function. if crc-multiframe mode is enabled, febeh/l works as submultiframe error indication counter (16 bits) which counts zeros in s i -bit position of frame 13 and 15 of every received crc multiframe. the error counter does not roll over. during alarm simulation, the counter is incremented once per submultiframe up to its saturation. clearing and updating the counter is done according to bit fmr1.ecm. if this bit is reset the error counter is permanently updated in the buffer. for correct read access of the error counter bit dec.debc has to be set. with the rising edge of this bit updating the buffer is stopped and the error counter is reset. bit dec.debc is reset automatically with reading the error counter high byte. if fmr1.ecm is set every second (interrupt isr3.sec) the error counter is latched and then automatically reset. the latched error counter state should be read within the next second. 70 ebcl eb7 eb0 (56) 70 ebch eb15 eb8 (57) falc ? 56 pef 2256 h/e e1 registers user?s manual 315 ds1.1, 2003-10-23 hardware description crc error counter 2 (read) cc(15:0) crc error counter (reported from te through s a 6 -bit) depending on bit lcr1.eprm the error counter increment is selected: lcr1.eprm = 0: if doubleframe format is selected, cec2h/l has no function. if crc-multiframe mode is enabled, cec2h/l works as s a 6-bit error indication counter (16 bits) which counts the s a 6-bit sequence 0001 and 0011in every received crc submultiframe. incrementing the counter is only possible in the multiframe synchronous state frs0.lmfa = 0. s a 6-bit sequence: sa61, sa62, sa63, sa64 = 0001 or 0011 where sa61 is received in frame 1 or 9 in every multiframe. during alarm simulation, the counter is incremented once per submultiframe up to its saturation. pseudo-random binary sequence error counter lcr1.eprm = 1: this 16-bit counter is incremented with every received prbs bit error in the prbs synchronous state rsp.llbad = 1. the error counter does not roll over. during alarm simulation, the counter is incremented continuously with every second received bit. clearing and updating the counter is done according to bit fmr1.ecm. if this bit is reset the error counter is permanently updated in the buffer. for correct read access of the error counter bit dec.dcec2 has to be set. with the rising edge of this bit updating of the buffer is stopped and the error counter is reset. bit dec.dcec2 is reset automatically with reading the error counter high byte. 70 cec2l cc7 cc0 (58) 70 cec2h cc15 cc8 (59) falc ? 56 pef 2256 h/e e1 registers user?s manual 316 ds1.1, 2003-10-23 hardware description if fmr1.ecm is set every second (interrupt isr3.sec) the error counter is latched and then reset automatically. the latched error counter state should be read within the next second. crc error counter 3 (read) ce(15:0) crc error counter (detected at t reference point in s a 6 -bit) gcr.ecmc = 0: if doubleframe format is selected, cec3h/l has no function. if crc-multiframe mode is enabled, cec3h/l works as s a 6-bit error indication counter (16 bits) which counts the s a 6-bit sequence 0010 and 0011in every received crc submultiframe. incrementing the counter is only possible in the multiframe synchronous state frs0.lmfa = 0. s a 6-bit sequence: sa61, sa62, sa63, sa64 = 0010 or 0011 where sa61 is received in frame 1 or 9 in every multiframe. the error counter does not roll over. during alarm simulation, the counter is incremented once per submultiframe up to its saturation. ce(7:2) multiframe counter gcr.ecmc = 1: this 6 bit counter increments with each multiframe period in the asynchronous state frs0.lfa/lmfa = 1. during alarm simulation, the counter is incremented once per multiframe up to its saturation. ce(1:0) change of frame alignment counter gcr.ecmc = 1: this 2 bit counter increments with each detected change of frame/multiframe alignment. the error counter does not roll over. during alarm simulation, the counter is incremented once per multiframe up to its saturation. clearing and updating the counter is done according to bit fmr1.ecm. 70 cec3l ce7 ce0 (5a) 70 cec3h ce15 ce8 (5b) falc ? 56 pef 2256 h/e e1 registers user?s manual 317 ds1.1, 2003-10-23 hardware description if this bit is reset the error counter is permanently updated in the buffer. for correct read access of the error counter bit dec.dcec3 has to be set. with the rising edge of this bit updating of the buffer is stopped and the error counter is reset. bit dec.dcec3 is reset automatically with reading the error counter high byte. if fmr1.ecm is set every second (interrupt isr3.sec) the error counter is latched and then automatically reset. the latched error counter state should be read within the next second. receive s a 4-bit register (read) rs4(7:0) receive s a 4-bit data (y-bits) rs5(7:0) receive s a 5-bit data rs6(7:0) receive s a 6-bit data rs7(7:0) receive s a 7-bit data rs8(7:0) receive s a 8-bit data this register contains the information of the eight s a x bits (x = 4 to 8) of the previously received crc multiframe. these registers are updated with every multiframe begin interrupt isr0.rmb. rs40 is received in bit-slot 4 of every service word in frame 1, rs47 in frame 15 rs50 is received in bit-slot 5, time slot 0, frame 1, rs57 in frame 15 rs60 is received in bit-slot 6, time slot 0, frame 1, rs67 in frame 15 rs70 is received in bit-slot 7, time slot 0, frame 1, rs77 in frame 15 rs80 is received in bit-slot 8, time slot 0, frame 1, rs87 in frame 15 valid if crc multiframe format is enabled by setting bits fmr2.rfs1 = 1 or fmr2.rfs(1:0) = 01 (doubleframe format). 70 rsa4 rs47 rs40 (5c) rsa5 rs57 rs50 (5d) rsa6 rs67 rs60 (5e) rsa7 rs77 rs70 (5f) rsa8 rs87 rs80 (60) falc ? 56 pef 2256 h/e e1 registers user?s manual 318 ds1.1, 2003-10-23 hardware description receive s a 6-bit status (read) four consecutive received s a 6-bits are checked on the by ets300233 defined s a 6-bit combinations. the falc ? 56 detects the following ?fixed? s a 6-bit combinations: sa61, sa62, sa63, sa64 = 1000, 1010, 1100, 1110, 1111. all other possible 4 bit combinations are grouped to status ?x?. a valid s a 6-bit combination must occur three times in a row. the corresponding status bit in this register is set. even if the detected status is active for a short time the status bit remains active until this register is read. reading the register resets all pending status information. with any change of state of the s a 6-bit combinations an interrupt status isr0.sa6sc is generated. during the basic frame asynchronous state updating of this register and interrupt status isr0.sa6sc is disabled. in multiframe format the detection of the s a 6-bit combinations can be done either synchronous or asynchronous to the submultiframe (fmr3.sa6sy). in synchronous detection mode updating of register rsa6s is done in the multiframe synchronous state (frs0.lmfa = 0). in asynchronous detection mode updating is independent to the multiframe synchronous state. s_x receive s a 6-bit status_x if none of the fixed s a 6-bit combinations are detected this bit is set. s_f receive s a 6-bit status: "1111" receive s a 6-bit status ?1111? is detected for three times in a row in the s a 6-bit positions. s_e receive s a 6-bit status: "1110" receive s a 6-bit status ?1110? is detected for three times in a row in the s a 6-bit positions. s_c receive s a 6-bit status: "1100" receive s a 6-bit status ?1100? is detected for three times in a row in the s a 6bit positions. 70 rsa6s s_x s_f s_e s_c s_a s_8 (61) falc ? 56 pef 2256 h/e e1 registers user?s manual 319 ds1.1, 2003-10-23 hardware description s_a receive s a 6-bit status: "1010" receive s a 6-bit status ?1010? is detected for three times in a row in the s a 6-bit positions. s_8 receive s a 6-bit status: "1000" receive s a 6-bit status ?1000? is detected for three times in a row in the s a 6-bit positions. receive signaling pointer 1 (read) value after reset: 00 h rs(8:1)c receive signaling register rs(8:1) changed a one in each bit position indicates that the received signaling data in the corresponding rs(8:1) registers are updated. bit rs1c is the pointer for register rs1, while rs8c points to rs8. receive signaling pointer 2 (read) value after reset: 00 h rs(16:9)c receive signaling register rs9-16 changed a one in each bit position indicates that the received signaling data in the corresponding rs9-16 registers are updated. bit rs9c is the pointer for register rs9, while rs16c points to rs16. 70 rsp1 rs8c rs7c rs6c rs5c rs4c rs3c rs2c rs1c (62) 70 rsp2 rs16c rs15c rs14c rs13c rs12c rs11c rs10c rs9c (63) falc ? 56 pef 2256 h/e e1 registers user?s manual 320 ds1.1, 2003-10-23 hardware description signaling status register (read) xdov transmit data overflow - hdlc channel 1 more than 32 bytes have been written to the xfifo. this bit is reset ? by a transmitter reset command xres ? when all bytes in the accessible half of the xfifo have been moved in the inaccessible half. xfw transmit fifo write enable - hdlc channel 1 data can be written to the xfifo. xrep transmission repeat - hdlc channel 1 status indication of cmdr.xrep. rli receive line inactive - hdlc channel 1 neither flags as interframe time fill nor frames are received through the signaling time slot. cec command executing - hdlc channel 1 0 = no command is currently executed, the cmdr register can be written to. 1 = a command (written previously to cmdr) is currently executed, no further command can be temporarily written in cmdr register. note: cec is active for about 2.5 periods of the current system data rate. sfs status freeze signaling 0 = freeze signaling status inactive. 1 = freeze signaling status active 70 sis xdov xfw xrep rli cec sfs (64) falc ? 56 pef 2256 h/e e1 registers user?s manual 321 ds1.1, 2003-10-23 hardware description receive signaling status register (read) rsis relates to the last received hdlc frame; it is copied into rfifo when end-of-frame is recognized (last byte of each stored frame). vfr valid frame - hdlc channel 1 determines whether a valid frame has been received. 1= valid 0 = invalid an invalid frame is either ? a frame which is not an integer number of 8 bits (n 8 bits) in length (e.g. 25 bits), or ? a frame which is too short taking into account the operation mode selected by mode (mds(2:0)) and the selection of receive crc on/off (ccr2.rcrc) as follows: mds(2:0) = 011 (16 bit address), rcrc = 0: 4 bytes; rcrc = 1: 3 or 4 bytes mds(2:0) = 010 (8 bit address), rcrc = 0: 3 bytes; rcrc = 1: 2 or 3 bytes note:shorter frames are not reported. rdo receive data overflow - hdlc channel 1 a rfifo data overflow has occurred during reception of the frame. additionally, an interrupt can be generated (refer to isr1.rdo/imr1.rdo). crc16 crc16 compare/check - hdlc channel 1 0 = crc check failed; received frame contains errors. 1 = crc check o.k.; received frame is error-free. rab receive message aborted - hdlc channel 1 this bit is set in ss7 mode, if the maximum number of octets (272+7) is exceeded. the received frame was aborted from the transmitting station. according to the hdlc protocol, this frame must be discarded by the receiver station. 70 rsis vfr rdo crc16 rab ha1 ha0 la (65) falc ? 56 pef 2256 h/e e1 registers user?s manual 322 ds1.1, 2003-10-23 hardware description ha1, ha0 high byte address compare - hdlc channel 1 significant only if 2-byte address mode or ss7 mode has been selected. in operating modes which provide high byte address recognition, the falc ? 56 compares the high byte of a 2-byte address with the contents of two individually programmable registers (rah1, rah2) and the fixed values fe h and fc h (broadcast address). depending on the result of this comparison, the following bit combinations are possible (ss7 support not active): 00 = rah2 has been recognized 01 = broadcast address has been recognized 10 = rah1 has been recognized c/r = 0 (bit 1) 11 = rah1 has been recognized c/r = 1 (bit 1) note: if rah1, rah2 contain identical values, a match is indicated by "10" or "11". if signaling system 7 support is activated (see mode register), the bit functions are defined as follows: 00 = not valid 01 = fill in signaling unit (fisu) detected 10 = link status signaling unit (lssu) detected 11 = message signaling unit (msu) detected la low byte address compare - hdlc channel 1 significant in hdlc modes only. the low byte address of a 2-byte address field, or the single address byte of a 1-byte address field is compared to two registers. (ral1, ral2). 0 = ral2 has been recognized 1 = ral1 has been recognized falc ? 56 pef 2256 h/e e1 registers user?s manual 323 ds1.1, 2003-10-23 hardware description receive byte count low - hdlc channel 1 (read) together with rbch, bits rbc(11:8), indicates the length of a received frame (1 to 4095 bytes). bits rbc(4:0) indicate the number of valid bytes currently in rfifo. these registers must be read by the cpu following a rme interrupt. received byte count high - hdlc channel 1 (read) value after reset: 000 xxxxx ov counter overflow - hdlc channel 1 more than 4095 bytes received. rbc(11:8) receive byte count - hdlc channel 1 (most significant bits) together with rbcl, bits rbc(7:0) indicates the length of the received frame. interrupt status register 0 (read) value after reset: 00 h all bits are reset when isr0 is read. if bit gcr.vis is set, interrupt statuses in isr0 are flagged although they are masked by register imr0. however, these masked interrupt statuses neither generate a signal on int, nor are visible in register gis. rme receive message end - hdlc channel 1 one complete message of length less than 32 bytes, or the last part of a frame at least 32 bytes long is stored in the receive fifo, including the status byte. 70 rbcl rbc7 rbc0 (66) 70 rbch ov rbc11 rbc10 rbc9 rbc8 (67) 70 isr0 rme rfs t8ms rmb casc crc4 sa6sc rpf (68) falc ? 56 pef 2256 h/e e1 registers user?s manual 324 ds1.1, 2003-10-23 hardware description the complete message length can be determined reading the rbch, rbcl registers, the number of bytes currently stored in rfifo is given by rbc(4:0). additional information is available in the rsis register. rfs receive frame start - hdlc channel 1 this is an early receiver interrupt activated after the start of a valid frame has been detected, i.e. after an address match (in operation modes providing address recognition), or after the opening flag (transparent mode 0) is detected, delayed by two bytes. after an rfs interrupt, the contents of ral1 rsis bits 3 to 1 are valid and can be read by the cpu. t8ms receive time out 8 ms only active if multiframing is enabled. the framer has found the double framing (basic framing) frs0.lfa = 0 and is searching for the multiframing. this interrupt is set to indicate that no multiframing was found within a time window of 8 ms. in multiframe synchronous state this interrupt is not generated. refer also to floating multiframe alignment window. rmb receive multiframe begin this bit is set with the beginning of a received crc multiframe related to the internal receive line timing. in crc multiframe format fmr2.rfs1 = 1 or in doubleframe format fmr2.rfs(1:0) = 01 this interrupt occurs every 2 ms. if fmr2.rfs(1:0) = 00 this interrupt is generated every doubleframe (512 bits). casc received cas information changed this bit is set with the updating of a received cas multiframe information in the registers rs(16:1). if the last received cas information is different to the previous received one, this interrupt is generated after update has been completed. this interrupt only occurs only in ts0 and ts16 synchronous state. the registers rs(16:1) should be read within the next 2 ms otherwise the contents is lost. falc ? 56 pef 2256 h/e e1 registers user?s manual 325 ds1.1, 2003-10-23 hardware description crc4 receive crc4 error 0 = no crc4 error occurs. 1 = the crc4 check of the last received submultiframe failed. sa6sc receive s a 6-bit status changed with every change of state of the received s a 6-bit combinations this interrupt is set. rpf receive pool full 32 bytes of a frame have arrived in the receive fifo. the frame is not yet completely received. interrupt status register 1 (read) all bits are reset when isr1 is read. if bit gcr.vis is set, interrupt statuses in isr1 are flagged although they are masked by register imr1. however, these masked interrupt statuses neither generate a signal on int, nor are visible in register gis. llbsc line loop-back status change depending on bit lcr1.eprm the source of this interrupt status changed: lcr1.eprm = 0: this bit is set, if the llb activate signal or the llb deactivate signal, respectively, is detected over a period of 25 ms with a bit error rate less than 10 -2 . the llbsc bit is also set, if the current detection status is left, i.e., if the bit error rate exceeds 10 -2 . the actual detection status can be read from the rsp.llbad and rsp.llbdd, respectively. prbs status change lcr1.eprm = 1: with any change of state of the prbs synchronizer this bit is set. the current status of the prbs synchronizer is indicated in rsp.llbad. 70 isr1 llbsc rdo alls xdu xmb suex xlsc xpr (69) falc ? 56 pef 2256 h/e e1 registers user?s manual 326 ds1.1, 2003-10-23 hardware description rdo receive data overflow - hdlc channel 1 this interrupt status indicates that the cpu did not respond fast enough to an rpf or rme interrupt and that data in rfifo has been lost. even when this interrupt status is generated, the frame continues to be received when space in the rfifo is available again. note: whereas the bit rsis.rdo in the frame status byte indicates whether an overflow occurred when receiving the frame currently accessed in the rfifo, the isr1.rdo interrupt status is generated as soon as an overflow occurs and does not necessarily pertain to the frame currently accessed by the processor. alls all sent - hdlc channel 1 this bit is set if the last bit of the current frame has been sent completely and xfifo is empty. this bit is valid in hdlc mode only. xdu transmit data underrun - hdlc channel 1 transmitted frame was terminated with an abort sequence because no data was available for transmission in xfifo and no xme was issued. note: transmitter and xfifo are reset and deactivated if this condition occurs. they are reactivated not before this interrupt status register has been read. thus, xdu should not be masked by register imr1. xmb transmit multiframe begin this bit is set every 2 ms with the beginning of a transmitted multiframe related to the internal transmit line interface timing. just before setting this bit registers xs(16:1) are copied in the transmit shift registers. the registers xs(16:1) are empty and has to be updated otherwise the contents is retransmitted. suex signaling unit error threshold exceeded - hdlc channel 1 masks the indication by interrupt that the selected error threshold for ss7 signaling units has been exceeded. 0 = signaling unit error count below selected threshold 1 = signaling unit error count exceeded selected threshold note: suex is only valid, if ss7 mode is selected. if suex is caused by an aborted/invalid frame, the interrupt will be issued regularly until a valid frame is received (e.g. a fisu). falc ? 56 pef 2256 h/e e1 registers user?s manual 327 ds1.1, 2003-10-23 hardware description xlsc transmit line status change xlsc is set with the rising edge of the bit frs1.xlo or with any change of bit frs1.xls. the actual status of the transmit line monitor can be read from the frs1.xls and frs1.xlo. xpr transmit pool ready - hdlc channel 1 a data block of up to 32 bytes can be written to the transmit fifo. xpr enables the fastest access to xfifo. it has to be used for transmission of long frames, back-to-back frames or frames with shared flags. interrupt status register 2 (read) all bits are reset when isr2 is read. if bit gcr.vis is set, interrupt statuses in isr2 are flagged although they are masked by register imr2. however, these masked interrupt statuses neither generate a signal on int, nor are visible in register gis. far frame alignment recovery the framer has reached doubleframe synchronization. set when bit frs0.lfa is reset. it is set also after alarm simulation is finished and the receiver is still synchronous. lfa loss of frame alignment the framer has lost synchronization and bit frs0.lfa is set. it is set during alarm simulation. mfar multiframe alignment recovery set when the framer has found two crc-multiframes at an interval of n 2 ms (n = 1, 2, 3, and so forth) without a framing error. at the same time bit frs0.lmfa is reset. it is set also after alarm simulation is finished and the receiver is still synchronous. only active if crc-multiframe format is selected. 70 isr2 far lfa mfar t400ms ais los rar ra (6a) falc ? 56 pef 2256 h/e e1 registers user?s manual 328 ds1.1, 2003-10-23 hardware description t400ms receive time out 400 ms only active if multiframing is enabled. the framer has found the doubleframes (basic framing) frs0.lfa = 0 and is searching for the multiframing. this interrupt is set to indicate that no multiframing was found within a time window of 400 ms after basic framing has been achieved. in multiframe synchronous state this interrupt is not generated. ais alarm indication signal this bit is set when an alarm indication signal is detected and bit frs0.ais is set. it is set during alarm simulation. if gcr.sci is set high this interrupt status bit is set with every change of state of frs0.ais. los loss-of-signal this bit is set when a loss-of-signal alarm is detected in the received bit stream and frs0.los is set. it is set during alarm simulation. if gcr.sci is set high this interrupt status bit is set with every change of state of frs0.los. rar remote alarm recovery set if a remote alarm in ts0 is cleared and bit frs0.rra is reset. it is set also after alarm simulation is finished and no remote alarm is detected. ra remote alarm set if a remote alarm in ts0 is detected and bit frs0.rra is set. it is set during alarm simulation. falc ? 56 pef 2256 h/e e1 registers user?s manual 329 ds1.1, 2003-10-23 hardware description interrupt status register 3 (read) all bits are reset when isr3 is read. if bit gcr.vis is set, interrupt statuses in isr3 are flagged although they are masked by register imr3. however, these masked interrupt statuses neither generate a signal on int, nor are visible in register gis. es errored second this bit is set if at least one enabled interrupt source by esm is set during the time interval of one second. interrupt sources of esm register: lfa = loss of frame alignment detected (frs0.lfa) fer = framing error received cer = crc error received ais = alarm indication signal (frs0.ais) los = loss-of-signal (frs0.los) cve = code violation detected slip = receive slip positive/negative detected ebe = e-bit error detected (rsp.rs13/15) sec second timer the internal one-second timer has expired. the timer is derived from clock rclk or external pin sec/fsc. lmfa16 loss of multiframe alignment ts 16 multiframe alignment of time slot 16 has been lost if two consecutive multiframe pattern are not detected or if in 16 consecutive time slot 16 all bits are reset. if register gcr.sci is high this interrupt status bit is set with every change of state of frs1.ts16lfa. ais16 alarm indication signal ts 16 status change the alarm indication signal ais in time slot 16 for the 64-kbit/s channel associated signaling is detected or cleared. a change in bit frs1.ts16ais sets this interrupt. (this bit is set if the incoming ts 16 signal contains less than 4 zeros in each of two consecutive ts16- multiframe periods.) 70 isr3 es sec lmfa16 ais16 ra16 rsn rsp (6b) falc ? 56 pef 2256 h/e e1 registers user?s manual 330 ds1.1, 2003-10-23 hardware description ra16 remote alarm time slot 16 status change a change in the remote alarm bit in cas multiframe alignment word is detected. rsn receive slip negative the frequency of the receive route clock is greater than the frequency of the receive system interface working clock based on 2.048 mhz. a frame is skipped. it is set during alarm simulation. rsp receive slip positive the frequency of the receive route clock is less than the frequency of the receive system interface working clock based on 2.048 mhz. a frame is repeated. it is set during alarm simulation. interrupt status register 4 (read) all bits are reset when isr4 is read. if bit gcr.vis is set, interrupt statuses in isr4 are flagged although they are masked by register imr4. however, these masked interrupt statuses neither generate a signal on int, nor are visible in register gis. xsp transmit slip positive the frequency of the transmit clock is less than the frequency of the transmit system interface working clock based on 2.048 mhz. a frame is repeated. after a slip has performed writing of register xc1 is not necessary. xsn transmit slip negative the frequency of the transmit clock is greater than the frequency of the transmit system interface working clock based on 2.048 mhz. a frame is skipped. after a slip has performed writing of register xc1 is not necessary. 70 isr4 xsp xsn rme2 rfs2 rdo2 alls2 xdu2 rpf2 (6c) falc ? 56 pef 2256 h/e e1 registers user?s manual 331 ds1.1, 2003-10-23 hardware description rme2 receive message end - hdlc channel 2 one complete message of length less than 32 bytes, or the last part of a frame at least 32 bytes long is stored in the receive fifo2, including the status byte. the complete message length can be determined reading register rbc2, the number of bytes currently stored in rfifo2 is given by rbc2(6:0). additional information is available in register rsis2. rfs2 receive frame start - hdlc channel 2 this is an early receiver interrupt activated after the start of a valid frame has been detected, i.e. after an address match (in operation modes providing address recognition), or after the opening flag (transparent mode 0) is detected, delayed by two bytes. after an rfs2 interrupt, the contents of ral1 rsis2 bits 3 to 1 are valid and can be read by the cpu. rdo2 receive data overflow - hdlc channel 2 this interrupt status indicates that the cpu did not respond fast enough to an rpf2 or rme2 interrupt and that data in rfifo2 has been lost. even when this interrupt status is generated, the frame continues to be received when space in the rfifo2 is available again. note: whereas the bit rsis2.rdo2 in the frame status byte indicates whether an overflow occurred when receiving the frame currently accessed in the rfifo2, the isr4.rdo2 interrupt status is generated as soon as an overflow occurs and does not necessarily pertain to the frame currently accessed by the processor. alls2 all sent - hdlc channel 2 this bit is set if the last bit of the current frame has been sent completely and xfifo2 is empty. this bit is valid in hdlc mode only. falc ? 56 pef 2256 h/e e1 registers user?s manual 332 ds1.1, 2003-10-23 hardware description xdu2 transmit data underrun - hdlc channel 2 transmitted frame was terminated with an abort sequence because no data was available for transmission in xfifo2 and no xme2 was issued. note: transmitter and xfifo2 are reset and deactivated if this condition occurs. they are reactivated not before this interrupt status register has been read. thus, xdu2 should not be masked via register imr4. rpf2 receive pool full - hdlc channel 2 32 bytes of a frame have arrived in the receive fifo2. the frame is not yet completely received. interrupt status register 5 (read) all bits are reset when isr5 is read. if bit gcr.vis is set, interrupt statuses in isr5 are flagged although they are masked via register imr5. however, these masked interrupt statuses neither generate a signal on int, nor are visible in register gis. xpr2 transmit pool ready - hdlc channel 2 a data block of up to 32 bytes can be written to the transmit fifo2. xpr2 enables the fastest access to xfifo2. it has to be used for transmission of long frames, back-to-back frames or frames with shared flags. xpr3 transmit pool ready - hdlc channel 3 a data block of up to 32 bytes can be written to the transmit fifo3. xpr3 enables the fastest access to xfifo3. it has to be used for transmission of long frames, back-to-back frames or frames with shared flags. 70 isr5 xpr2 xpr3 rme3 rfs3 rdo3 alls3 xdu3 rpf3 (6d) falc ? 56 pef 2256 h/e e1 registers user?s manual 333 ds1.1, 2003-10-23 hardware description rme3 receive message end - hdlc channel 3 one complete message of length less than 32 bytes, or the last part of a frame at least 32 bytes long is stored in the receive fifo3, including the status byte. the complete message length can be determined reading register rbc3, the number of bytes currently stored in rfifo3 is given by rbc3(6:0). additional information is available in register rsis3. rfs3 receive frame start - hdlc channel 3 this is an early receiver interrupt activated after the start of a valid frame has been detected, i.e. after an address match (in operation modes providing address recognition), or after the opening flag (transparent mode 0) is detected, delayed by two bytes. after an rfs2 interrupt, the contents of ral1 rsis3 bits 3 to 1 are valid and can be read by the cpu. rdo3 receive data overflow - hdlc channel 3 this interrupt status indicates that the cpu did not respond fast enough to an rpf3 or rme3 interrupt and that data in rfifo3 has been lost. even when this interrupt status is generated, the frame continues to be received when space in the rfifo3 is available again. note: whereas the bit rsis3.rdo3 in the frame status byte indicates whether an overflow occurred when receiving the frame currently accessed in the rfifo3, the isr5.rdo3 interrupt status is generated as soon as an overflow occurs and does not necessarily pertain to the frame currently accessed by the processor. alls3 all sent - hdlc channel 3 this bit is set if the last bit of the current frame has been sent completely and xfifo3 is empty. this bit is valid in hdlc mode only. falc ? 56 pef 2256 h/e e1 registers user?s manual 334 ds1.1, 2003-10-23 hardware description xdu3 transmit data underrun - hdlc channel 3 transmitted frame was terminated with an abort sequence because no data was available for transmission in xfifo3 and no xme3 was issued. note: transmitter and xfifo3 are reset and deactivated if this condition occurs. they are reactivated not before this interrupt status register has been read. thus, xdu3 should not be masked via register imr5. rpf3 receive pool full - hdlc channel 3 32 bytes of a frame have arrived in the receive fifo3. the frame is not yet completely received. falc ? 56 pef 2256 h/e e1 registers user?s manual 335 ds1.1, 2003-10-23 hardware description global interrupt status register (read) value after reset: 00 h plll system pll lock status 0 = pll is unlocked. 1 = pll is locked. isr5 pending interrupt(s) in interrupt status register 5 0 = no pending interrupt. 1 = at least one interrupt is pending. isr4 pending interrupt(s) in interrupt status register 4 0 = no pending interrupt. 1 = at least one interrupt is pending. isr3 pending interrupt(s) in interrupt status register 3 0 = no pending interrupt. 1 = at least one interrupt is pending. isr2 pending interrupt(s) in interrupt status register 2 0 = no pending interrupt. 1 = at least one interrupt is pending. isr1 pending interrupt(s) in interrupt status register 1 0 = no pending interrupt. 1 = at least one interrupt is pending. isr0 pending interrupt(s) in interrupt status register 0 0 = no pending interrupt. 1 = at least one interrupt is pending. 70 gis plll isr5 isr4 isr3 isr2 isr1 isr0 (6e) falc ? 56 pef 2256 h/e e1 registers user?s manual 336 ds1.1, 2003-10-23 hardware description receive cas register (read) value after reset: not defined receive cas register (16:1) each register except rs1 contains the received cas bits for two time slots. the received cas multiframe is compared to the previously received one. if the contents changed a cas multiframe changed interrupt (isr0.casc) is generated and informs the user that a new multiframe has to be read within the next 2 ms. if requests for reading the rs(16:1) register are ignored, the received da ta is lost. rs1 contains frame 0 of the cas multiframe. msb is received first. additionally a receive signaling data change pointer indicates an update of register rs(16:1). refer also to register rsp(2:1). access to rs(16:1) registers is only valid if the serial receive signaling access on the system highway is disabled. table 66 receive cas registers (e1) 70 rs1 0 0 0 0 x y x x (70) rs2 a1 b1 c1 d1 a16 b16 c16 d16 (71) rs3 a2 b2 c2 d2 a17 b17 c17 d17 (72) rs4 a3 b3 c3 d3 a18 b18 c18 d18 (73) rs5 a4 b4 c4 d4 a19 b19 c19 d19 (74) rs6 a5 b5 c5 d5 a20 b20 c20 d20 (75) rs7 a6 b6 c6 d6 a21 b21 c21 d21 (76) rs8 a7 b7 c7 d7 a22 b22 c22 d22 (77) rs9 a8 b8 c8 d8 a23 b23 c23 d23 (78) rs10 a9 b9 c9 d9 a24 b24 c24 d24 (79) rs11 a10 b10 c10 d10 a25 b25 c25 d25 (7a) rs12 a11 b11 c11 d11 a26 b26 c26 d26 (7b) rs13 a12 b12 c12 d12 a27 b27 c27 d27 (7c) rs14 a13 b13 c13 d13 a28 b28 c28 d28 (7d) rs15 a14 b14 c14 d14 a29 b29 c29 d29 (7e) rs16 a15 b15 c15 d15 a30 b30 c30 d30 (7f) falc ? 56 pef 2256 h/e e1 registers user?s manual 337 ds1.1, 2003-10-23 hardware description receive byte count register 2 (read) value after reset: 00 h ov2 counter overflow - hdlc channel 2 0 = less than or equal to 128 bytes received 1 = more than 128 bytes received rbc2(6:0) receive byte count - hdlc channel 2 indicates the length of a received frame. receive byte count register 3 (read) value after reset: 00 h ov3 counter overflow - hdlc channel 3 0 = less than or equal to 128 bytes received 1 = more than 128 bytes received rbc3(6:0) receive byte count - hdlc channel 3 indicates the length of a received frame. signaling status register 2 (read) value after reset: 00 h xdov2 transmit data overflow - hdlc channel 2 more than 32 bytes have been written to the xfifo2. this bit is reset by a transmitter reset command xres or when all bytes in the accessible half of the xfifo2 have been moved in the inaccessible half. 70 rbc2 ov2 rbc26 rbc25 rbc24 rbc23 rbc22 rbc21 rbc20 (90) 70 rbc3 ov3 rbc36 rbc35 rbc34 rbc33 rbc32 rbc31 rbc30 (91) 70 sis2 xdov2 xfw2 xrep2 rli2 cec2 (a9) falc ? 56 pef 2256 h/e e1 registers user?s manual 338 ds1.1, 2003-10-23 hardware description xfw2 transmit fifo write enable - hdlc channel 2 data can be written to the xfifo2. xrep2 transmission repeat - hdlc channel 2 status indication of cmdr2.xrep2. rli2 receive line inactive - hdlc channel 2 neither flags as interframe time fill nor frames are received via the signaling time slot. cec2 command executing - hdlc channel 2 0 = no command is currently executed, the cmdr3 register can be written to. 1 = a command (written previously to cmdr3) is currently executed, no further command can be temporarily written in cmdr3 register. note:cec2 will be active at most 2.5 periods of the current system data rate. falc ? 56 pef 2256 h/e e1 registers user?s manual 339 ds1.1, 2003-10-23 hardware description receive signaling status register 2 (read) value after reset: 00 h rsis2 relates to the last received hdlc channel 2 frame; it is copied into rfifo2 when end-of-frame is recognized (last byte of each stored frame). vfr2 valid frame - hdlc channel 2 determines whether a valid frame has been received. 1 = valid 0 = invalid an invalid frame is either ? a frame which is not an integer number of 8 bits (n 8 bits) in length (e.g. 25 bits), or ? a frame which is too short taking into account the operation mode selected via mode2 (mds2(2:0)) and the selection of receive crc on/off (ccr3.rcrc2) as follows: mds2(2:0)=011 (16 bit address), rcrc2=0: 4 bytes; rcrc2=1: 3 or 4 bytes mds2(2:0)=010 (8 bit address), rcrc2=0: 3 bytes; rcrc2=1: 2 or 3 bytes note:shorter frames are not reported. rdo2 receive data overflow - hdlc channel 2 a data overflow has occurred during reception of the frame. additionally, an interrupt can be generated (refer to isr4.rdo2/imr4.rdo2). crc162 crc16 compare/check - hdlc channel 2 0 = crc check failed; received frame contains errors. 1 = crc check o.k.; received frame is error-free. rab2 receive message aborted - hdlc channel 2 this bit is set, if more than 5 contiguous 1-bits are detected. 70 rsis2 vfr2 rdo2 crc162 rab2 ha12 ha02 la2 (aa) falc ? 56 pef 2256 h/e e1 registers user?s manual 340 ds1.1, 2003-10-23 hardware description ha12, ha02 high byte address compare - hdlc channel 2 significant only if 2-byte address mode is selected. in operating modes which provide high byte address recognition, the falc ? compares the high byte of a 2-byte address with the contents of two individually programmable registers (rah1, rah2) and the fixed values fe h and fc h (broadcast address). depending on the result of this comparison, the following bit combinations are possible: 00 = rah2 has been recognized 01 = broadcast address has been recognized 10 = rah1 has been recognized c/r=0 (bit 1) 11 = rah1 has been recognized c/r=1 (bit 1) note: if rah1, rah2 contain identical values, a match is indicated by "10" or "11". la2 low byte address compare - hdlc channel 2 significant in hdlc modes only. the low byte address of a 2-byte address field, or the single address byte of a 1-byte address field is compared with two registers. (ral1, ral2). 0 = ral2 has been recognized 1 = ral1 has been recognized signaling status register 3 (read) value after reset: 00 h xdov3 transmit data overflow - hdlc channel 3 more than 32 bytes have been written to the xfifo3. this bit is reset by a transmitter reset command xres or when all bytes in the accessible half of the xfifo3 have been moved in the inaccessible half. xfw3 transmit fifo write enable - hdlc channel 3 data can be written to the xfifo3. 70 sis3 xdov3 xfw3 xrep3 rli3 cec3 (9a) falc ? 56 pef 2256 h/e e1 registers user?s manual 341 ds1.1, 2003-10-23 hardware description xrep3 transmission repeat - hdlc channel 3 status indication of cmdr3.xrep3. rli3 receive line inactive - hdlc channel 3 neither flags as interframe time fill nor frames are received via the signaling time slot. cec3 command executing - hdlc channel 3 0 = no command is currently executed, the cmdr4 register can be written to. 1 = a command (written previously to cmdr4) is currently executed, no further command can be temporarily written in cmdr4 register. note:cec3 will be active up to 2.5 periods of the current system data rate. receive signaling status register 3 (read) value after reset: 00 h rsis3 relates to the last received hdlc channel 3 frame; it is copied into rfifo3 when end-of-frame is recognized (last byte of each stored frame). vfr3 valid frame - hdlc channel 3 determines whether a valid frame has been received. 1 = valid 0 = invalid an invalid frame is either ? a frame which is not an integer number of 8 bits (n 8 bits) in length (e.g. 25 bits), or ? a frame which is too short taking into account the operation mode selected via mode3 (mds3(2:0)) and the selection of receive crc on/off (ccr4.rcrc3) as follows: mds3(2:0)=011 (16 bit address), rcrc3=0: 4 bytes; rcrc3=1: 3 or 4 bytes mds3(2:0)=010 (8 bit address), rcrc3=0: 3 bytes; rcrc3=1: 2 or 3 bytes 70 rsis3 vfr3 rdo3 crc163 rab3 ha13 ha03 la3 (9b) falc ? 56 pef 2256 h/e e1 registers user?s manual 342 ds1.1, 2003-10-23 hardware description note:shorter frames are not reported. rdo3 receive data overflow - hdlc channel 3 a data overflow has occurred during reception of the frame. additionally, an interrupt can be generated (refer to isr5.rdo3/imr5.rdo3). crc163 crc16 compare/check - hdlc channel 3 0 = crc check failed; received frame contains errors. 1 = crc check o.k.; received frame is error-free. rab3 receive message aborted - hdlc channel 3 this bit is set, if more than 5 contiguous 1-bits are detected. ha13, ha03 high byte address compare - hdlc channel 3 significant only if 2-byte address mode is selected. in operating modes which provide high byte address recognition, the falc ? compares the high byte of a 2-byte address with the contents of two individually programmable registers (rah1, rah2) and the fixed values fe h and fc h (broadcast address). depending on the result of this comparison, the following bit combinations are possible: 00 = rah2 has been recognized 01 = broadcast address has been recognized 10 = rah1 has been recognized c/r=0 (bit 1) 11 = rah1 has been recognized c/r=1 (bit 1) note:if rah1, rah2 contain identical values, a match is indicated by "10" or "11". la3 low byte address compare - hdlc channel 3 significant in hdlc modes only. the low byte address of a 2-byte address field, or the single address byte of a 1-byte address field is compared with two registers. (ral1, ral2). 0 = ral2 has been recognized 1 = ral1 has been recognized falc ? 56 pef 2256 h/e e1 registers user?s manual 343 ds1.1, 2003-10-23 hardware description receive fifo 2 (read) value after reset: 00 h rf(15:0) receive fifo - hdlc channel 2 the function is equivalent to rfifo of hdlc channel 1. receive fifo 3 (read) value after reset: 00 h rf(15:0) receive fifo - hdlc channel 3 the function is equivalent to rfifo of hdlc channel 1. multifunction port input status register (read) value after reset: xx h rpd port rpd input status rpc port rpc input status rpb port rpb input status rpa port rpa input status xpd port xpd input status xpc port xpc input status xpb port xpb input status xpa port xpa input status 70 rfifo2 rf7 rf0 (9c) rfifo2 rf15 rf8 (9d) 70 rfifo3 rf7 rf0 (9e) rfifo3 rf15 rf8 (9f) 70 mfpi rpd rpc rpb rpa xpd xpc xpb xpa (ab) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 344 ds1.1, 2003-10-23 hardware description 10 t1/j1 registers 10.1 t1/j1 control register addresses table 67 t1/j1 control register address arrangement address register type comment page 00 xfifo w transmit fifo 348 01 xfifo w transmit fifo 348 02 cmdr w command register 348 03 mode r/w mode register 350 04 rah1 r/w receive address high 1 351 05 rah2 r/w receive address high 2 351 06 ral1 r/w receive address low 1 351 07 ral2 r/w receive address low 2 352 08 ipc r/w interrupt port configuration 352 09 ccr1 r/w common configuration register 1 353 0a ccr2 r/w common configuration register 2 356 0c rtr1 r/w receive time slot register 1 357 0d rtr2 r/w receive time slot register 2 357 0e rtr3 r/w receive time slot register 3 357 0f rtr4 r/w receive time slot register 4 357 10 ttr1 r/w transmit time slot register 1 358 11 ttr2 r/w transmit time slot register 2 358 12 ttr3 r/w transmit time slot register 3 358 13 ttr4 r/w transmit time slot register 4 358 14 imr0 r/w interrupt mask register 0 359 15 imr1 r/w interrupt mask register 1 359 16 imr2 r/w interrupt mask register 2 359 17 imr3 r/w interrupt mask register 3 359 18 imr4 r/w interrupt mask register 4 359 19 imr5 r/w interrupt mask register 5 359 1b ierr r/w single bit error insertion register 360 1c fmr0 r/w framer mode register 0 360 falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 345 ds1.1, 2003-10-23 hardware description 1d fmr1 r/w framer mode register 1 362 1e fmr2 r/w framer mode register 2 364 1f loop r/w channel loop-back 367 20 fmr4 r/w framer mode register 4 368 21 fmr5 r/w framer mode register 5 370 22 xc0 r/w transmit control 0 371 23 xc1 r/w transmit control 1 372 24 rc0 r/w receive control 0 373 25 rc1 r/w receive control 1 375 26 xpm0 r/w transmit pulse mask 0 377 27 xpm1 r/w transmit pulse mask 1 377 28 xpm2 r/w transmit pulse mask 2 377 2b idle r/w idle channel code 378 2c xdl1 r/w transmit dl-bit register 1 378 2d xdl2 r/w transmit dl-bit register 2 378 2e xdl3 r/w transmit dl-bit register 3 378 2f ccb1 r/w clear channel register 1 379 30 ccb2 r/w clear channel register 2 379 31 ccb3 r/w clear channel register 3 379 32 icb1 r/w idle channel register 1 380 33 icb2 r/w idle channel register 2 380 34 icb3 r/w idle channel register 3 380 36 lim0 r/w line interface mode 0 380 37 lim1 r/w line interface mode 1 383 38 pcd r/w pulse count detection 384 39 pcr r/w pulse count recovery 385 3a lim2 r/w line interface register 2 386 3b lcr1 r/w loop code register 1 387 3c lcr2 r/w loop code register 2 389 3d lcr3 r/w loop code register 3 389 table 67 t1/j1 control register address arrangement (cont?d) address register type comment page falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 346 ds1.1, 2003-10-23 hardware description 3e sic1 r/w system interface control 1 390 3f sic2 r/w system interface control 2 391 40 sic3 r/w system interface control 3 393 44 cmr1 r/w clock mode register 1 395 45 cmr2 r/w clock mode register 2 396 46 gcr r/w global configuration register 1 399 47 esm r/w errored second mask 400 48 cmr3 r/w clock mode register 3 400 60 dec w disable error counter 400 70 xs1 w transmit signaling register 1 401 71 xs2 w transmit signaling register 2 401 72 xs3 w transmit signaling register 3 401 73 xs4 w transmit signaling register 4 401 74 xs5 w transmit signaling register 5 401 75 xs6 w transmit signaling register 6 401 76 xs7 w transmit signaling register 7 401 77 xs8 w transmit signaling register 8 401 78 xs9 w transmit signaling register 9 401 79 xs10 w transmit signaling register 10 401 7a xs11 w transmit signaling register 11 401 7b xs12 w transmit signaling register 12 401 80 pc1 r/w port configuration 1 402 81 pc2 r/w port configuration 2 402 82 pc3 r/w port configuration 3 402 83 pc4 r/w port configuration 4 402 84 pc5 r/w port configuration 5 405 85 gpc1 r/w global port configuration 1 406 86 pc6 r/w port configuration 6 407 x87 cmdr2 w command register 2 408 88 cmdr3 w command register 3 408 table 67 t1/j1 control register address arrangement (cont?d) address register type comment page falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 347 ds1.1, 2003-10-23 hardware description after reset all control registers except the xfifo and xs(12:1) are initialized to defined values. unused bits have to be cleared. 89 cmdr4 w command register 4 409 8b ccr3 r/w common control register 3 410 8c ccr4 r/w common control register 4 412 x8d ccr5 r/w common control register 5 413 8e mode2 r/w mode register 2 414 8f mode3 r/w mode register 3 415 92 gcm1 r/w global counter mode 1 416 93 gcm2 r/w global counter mode 2 416 94 gcm3 r/w global counter mode 3 416 95 gcm4 r/w global counter mode 4 416 96 gcm5 r/w global counter mode 5 417 97 gcm6 r/w global counter mode 6 417 98 gcm7 r/w global counter mode 7 417 99 gcm8 r/w global counter mode 8 417 9c xfifo2 w transmit fifo 2 418 9d xfifo2 w transmit fifo 2 418 9e xfifo3 w transmit fifo 3 418 9f xfifo3 w transmit fifo 3 418 a0 tseo r/w time slot even/odd select 419 a1 tsbs1 r/w time slot bit select 1 420 a2 tsbs2 r/w time slot bit select 2 420 a3 tsbs3 r/w time slot bit select 3 421 a4 tss2 r/w time slot select 2 421 a5 tss3 r/w time slot select 2 422 a8 tpc0 r/w test pattern control register 0 422 af glc1 r/w global line control register 1 423 table 67 t1/j1 control register address arrangement (cont?d) address register type comment page falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 348 ds1.1, 2003-10-23 hardware description note: read access to unused register addresses: value should be ignored. write access to unused register addresses: should be avoided, or set to 00 h in address range up to af h ; must be avoided in address range above af h if not defined elsewhere. 10.2 detailed description of t1/j1 control registers transmit fifo - hdlc channel 1 (write) writing data to xfifo of hdlc channel 1 can be done in 8-bit (byte) or 16-bit (word) access. the lsb is transmitted first. up to 32 bytes/16 words of transmit data can be written to the xfifo following an xpr interrupt. command register (write) value after reset: 00 h rmc receive message complete - hdlc channel 1 confirmation from cpu to falc ? 56 that the current frame or data block has been fetched following an rpf or rme interrupt, thus the occupied space in the rfifo can be released. if rmc is given while rfifo is already cleared, the next incoming data block is cleared instantly, although interrupts are generated. rres receiver reset the receive line interface except the clock and data recovery unit (dpll), the receive framer, the one-second timer and the receive signaling controller are reset. however the contents of the control registers is not deleted. xrep transmission repeat - hdlc channel 1 70 xfifo xf7 xf0 (00) xfifo xf15 xf8 (01) 70 cmdr rmc rres xrep xres xhf xtf xme sres (02) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 349 ds1.1, 2003-10-23 hardware description if xrep is set together with xtf (write 24h to cmdr), the falc ? 56 repeatedly transmits the contents of the xfifo (1 to 32 bytes) without hdlc framing fully transparently, i.e. without flag, crc. the cyclic transmission is stopped with an sres command or by resetting xrep. note: during cyclic transmission the xrep-bit has to be set with every write operation to cmdr. xres transmitter reset the transmit framer and transmit line interface excluding the system clock generator and the pulse shaper are reset. however the contents of the control registers is not deleted. xhf transmit hdlc frame - hdlc channel 1 after having written up to 32 bytes to the xfifo, this command initiates the transmission of a hdlc frame. xtf transmit transparent frame - hdlc channel 1 initiates the transmission of a transparent frame without hdlc framing. xme transmit message end - hdlc channel 1 indicates that the data block written last to the transmit fifo completes the current frame. the falc ? 56 can terminate the transmission operation properly by appending the crc and the closing flag sequence to the data. sres signaling transmitter reset - hdlc channel 1 the transmitter of the signaling controller is reset. xfifo is cleared of any data and an abort sequence (seven 1s) followed by interframe time fill is transmitted. in response to xres an xpr interrupt is generated. this command can be used by the cpu to abort a frame currently in transmission. note: the maximum time between writing to the cmdr register and the execution of the command takes 2.5 periods of the current system data rate. therefore, if the cpu operates with a very high clock rate in comparison with the falc ? 56's clock, it is recommended that bit sis.cec should be checked before writing to the cmdr register to avoid any loss of commands. if sclkx is used to clock the transmission path, commands to the hdlc transmitter should only be sent while this clock is falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 350 ds1.1, 2003-10-23 hardware description available. if sclkx is missing, the command register is blocked after an hdlc command is given. mode register (read/write) value after reset: 00 h mds(2:0) mode select - hdlc channel 1 the operating mode of the hdlc controller is selected. 000 = reserved 001 = signaling system 7 (ss7) support 1) 010 = one-byte address comparison mode (ral1, 2) 011 = two-byte address comparison mode (rah1, 2 and ral1, 2) 100 = no address comparison 101 = one-byte address comparison mode (rah1, 2) 110 = reserved 111 = no hdlc framing mode 1 brac bom receiver active - hdlc channel 1 switches the bom receiver to operational or inoperational state. 0 = receiver inactive 1 = receiver active hrac receiver active - hdlc channel 1 switches the hdlc receiver to operational or inoperational state. 0 = receiver inactive 1 = receiver active div data inversion - hdlc channel 1 setting this bit inverts the internal generated hdlc channel 1 data stream. 0 = normal operation, hdlc data stream not inverted 1 = hdlc data stream inverted 70 mode mds2 mds1 mds0 brac hrac div hdlci (03) 1) ccr2.radd must be set, if ss7 mode is selected falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 351 ds1.1, 2003-10-23 hardware description hdlci inverse hdlc operation - hdlc channel 1 setting this bit selects the hdlc channel 1 operation mode. 0 = normal operation, hdlc attached to line side 1 = inverse operation, hdlc attached to system side. hdlc data is received on xdi and transmitted on rdo. transmit time slot configuration is done in rtr(4:1), receive time slot configurarion is done in ttr(4:1). receive address byte high register 1 (read/write) value after reset: fd h in operating modes that provide high byte address recognition, the high byte of the received address is compared to the individually programmable values in rah1 and rah2. the address registers are used by all hdlc channels in common. rah1 value of the first individual high address byte bit 1 (c/r-bit) is excluded from address comparison. receive address byte high register 2 (read/write) value after reset: ff h rah2 value of second individual high address byte receive address byte low register 1 (read/write) value after reset: ff h 710 rah1 0 (04) 70 rah2 (05) 70 ral1 (06) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 352 ds1.1, 2003-10-23 hardware description ral1 value of first individual low address byte receive address byte low register 2 (read/write) value after reset: ff h ral2 value of the second individually programmable low address byte. interrupt port configuration (read/write) value after reset: 00 h unused bits have to be cleared. ssyf select sync frequency only applicable in master mode (lim0.mas = 1) and bit cmr2.dcf is cleared. 0 = reference clock on port sync is 1.544/2.048 mhz (see lim1.dcoc) 1 = reference clock on port sync is 8 khz ic0, ic1 interrupt port configuration these bits define the function of the interrupt output stage (pin int): 70 ral2 (07) 70 ipc ssyf ic1 ic0 (08) ic1 ic0 function x 0 1 0 1 1 open drain output push/pull output, active low push/pull output, active high falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 353 ds1.1, 2003-10-23 hardware description common configuration register 1 (read/write) value after reset: 00 h rscc rsc interrupt for cleared channels 0 = rsc interrupt is generated for all channels. 1 = rsc interrupt is generated only for those channels, that are not cleared. brm bom receive mode - hdlc channel 1 (significant in bom mode only) 0 = 10-byte packets 1 = continuous reception edlx enable dl-bit access through the transmit fifo - hdlc channel 1 a one in this bit position enables the internal dl-bit access through the receive/transmit fifo of the signaling controller. fmr1.edl has to be cleared. eits enable internal time slot 0 to 31 signaling - hdlc channel 1 0 = internal signaling in time slots 0 to 31 defined by registers rtr(4:1) or ttr(4:1) is disabled. 1 = internal signaling in time slots 0 to 31 defined by registers rtr(4:1) or ttr(4:1) is enabled. itf interframe time fill - hdlc channel 1 determines the idle (= no data to be sent) state of the transmit data coming from the signaling controller. 0 = continuous logical 1 is output 1 = continuous flag sequences are output (01111110 bit patterns) xmfa transmit multiframe aligned - hdlc channel 1 determines the synchronization between the framer and the corresponding signaling controller. 0 = the contents of the xfifo is transmitted without multiframe alignment. 1 = the contents of the xfifo is transmitted multiframe aligned. if ccr1.edlxis set, transmission of dl-bits is started in f72 70 ccr1 rscc brm edlx eits itf xmfa rft1 rft0 (09) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 354 ds1.1, 2003-10-23 hardware description format with frame 26. the first byte in xfifo is transmitted in the first time slot selected by ttr(4:1) and so on. after receiving a complete multiframe in the time slot mode (rtr(4:1)) an isr0.rme interrupt is generated, if no hdlc or bom mode is enabled. in dl-bit access (ccr1.edlx/eits = 10) xmfa is not valid. note: during the transmission of the xfifo content, the sypx or xmfs interval time should not be changed, otherwise the xfifo data has to be retransmitted. falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 355 ds1.1, 2003-10-23 hardware description rft(1:0) rfifo threshold level - hdlc channel 1 the size of the accessible part of rfifo can be determined by programming these bits. the number of valid bytes after an rpf interrupt is given in the following table: the value of rft 1,0 can be changed dynamically ? if reception is not running or ? after the current data block has been read, but before the command cmdr.rmc is issued (interrupt controlled data transfer). note:it is seen that changing the value of rft1,0 is possible even during the reception of one frame. the total length of the received frame can be always read directly in rbcl, rbch after an rpf interrupt, except when the threshold is increased during reception of that frame. the real length can then be inferred by noting which bit positions in rbcl are reset by an rmc command (see table below ): rft1 rft0 size of accessible part of rfifo 0 0 1 1 0 1 0 1 32 bytes (reset value) 16 bytes 4 bytes 2 bytes rft1 rft0 bit positions in rbcl reset by a cmdr.rmc command 0 0 1 1 0 1 0 1 rbc(4:0) rbc(3:0) rbc(1:0) rbc0 falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 356 ds1.1, 2003-10-23 hardware description common configuration register 2 (read/write) value after reset: 00 h unused bits have to be cleared. radd receive address pushed to rfifo - hdlc channel 1 if this bit is set, the received hdlc address information (1 or 2 bytes, depending on the address mode selected by mode.mds0) is pushed to rfifo. this function is applicable in non-auto mode and transparent mode 1. radd must be set, if ss7 mode is selected. rbfe receive bom filter enable - hdlc channel 1 setting this bit the bit oriented message (bom) receiver only accepts bom frames after detecting 7 out of 10 equal bom pattern. the bom pattern is stored in the rfifo adding a receive status byte marking a bom frame (rsis.hfr) and an interrupt isr0.rme is generated. the current state of the bom receiver is indicated in register sis.ivb. when the valid bom pattern disappears an interrupt isr0.biv is generated. rcrc receive crc on/off - hdlc channel 1 only applicable in non-auto mode. if this bit is set, the received crc checksum is written to rfifo (crc-itu-t: 2 bytes). the checksum, consisting of the 2 last bytes in the received frame, is followed in the rfifo by the status information byte (contents of register rsis). the received crc checksum is additionally checked for correctness. if non-auto mode is selected, the limits for ?valid frame? check are modified (refer to rsis.vfr). xcrc transmit crc on/off - hdlc channel 1 if this bit is set, the crc checksum is not generated internally. it has to be written as the last two bytes in the transmit fifo (xfifo). the transmitted frame is closed automatically with a closing flag. note: the falc ? 56 does not check whether the length of the frame, i.e., the number of bytes to be transmitted, makes sense or not. 70 ccr2 radd rbfe rcrc xcrc (0a) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 357 ds1.1, 2003-10-23 hardware description receive time slot register 1 to 4 (read/write) value after reset: 00 h , 00 h , 00 h , 00 h ts(31:0) time slot register these bits define the received time slots on the system highway port rdo to be extracted. additionally these registers control the rsigm marker which can be forced high during the corresponding time slots independently of bit ccr1.eits. a one in the rtr(4:1) bits samples the corresponding time slot in the rfifo of the signaling controller, if bit ccr1.eits is set. assignments: sic2.ssc2 = 0: (32 time slots/frame) ts0 time slot 0,ts31 time slot 31 sic2.ssc2 = 1: (24 time slots/frame) ts0 time slot 0,ts23 time slot 23 0 = the corresponding time slot is not extracted and stored in the rfifo. 1 = the contents of the selected time slot is stored in the rfifo. although the idle time slots can be selected. this function is only active, if bits ccr1.eits is set. the corresponding time slot is forced high on pin rsigm. 70 rtr1 ts0 ts1 ts2 ts3 ts4 ts5 ts6 ts7 (0c) rtr2 ts8 ts9 ts10 ts11 ts12 ts13 ts14 ts15 (0d) rtr3 ts16 ts17 ts18 ts19 ts20 ts21 ts22 ts23 (0e) rtr4 ts24 ts25 ts26 ts27 ts28 ts29 ts30 ts31 (0f) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 358 ds1.1, 2003-10-23 hardware description transmit time slot register 1 to 4 (read/write) value after reset: 00 h , 00 h , 00 h , 00 h ts(31:0) transmit time slot register these bits define the transmit time slots on the system highway to be inserted. additionally these registers control the xsigm marker which can be forced high during the corresponding time slots independently of bit ccr1.eits. a one in the ttr(4:1) bits inserts the corresponding time slot sourced by the xfifo in the data received on pin xdi, if bit ccr1.eits is set. if sic3.ttrf is set and ccr1.edlx/eits = 00, insertion of data received on port xsig is controlled by this registers. assignments: sic2.ssc2 = 0: (32 time slots/frame) ts0 time slot 0, ts31 time slot 31 sic2.ssc2 = 1: (24 time slots/frame) ts0 time slot 0, ts23 time slot 23 0 = the selected time slot is not inserted into the outgoing data stream. 1 = the contents of the selected time slot is inserted into the outgoing data stream from xfifo. this function is only active, if bits ccr1.eits is set. the corresponding time slot are forced high on marker pin xsigm. 70 ttr1 ts0 ts1 ts2 ts3 ts4 ts5 ts6 ts7 (10) ttr2 ts8 ts9 ts10 ts11 ts12 ts13 ts14 ts15 (11) ttr3 ts16 ts17 ts18 ts19 ts20 ts21 ts22 ts23 (12) ttr4 ts24 ts25 ts26 ts27 ts28 ts29 ts30 ts31 (13) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 359 ds1.1, 2003-10-23 hardware description interrupt mask registers value after reset: ff h , ff h , ff h , ff h ,ff h imr(5:0) interrupt mask register each interrupt source can generate an interrupt signal on port int (characteristics of the output stage are defined by register ipc). a ?1? in a bit position of imr(5:0) sets the mask active for the interrupt status in isr(5:0). masked interrupt statuses neither generate a signal on int, nor are they visible in register gis. moreover, they are ? not displayed in the interrupt status register if bit gcr.vis is cleared ? displayed in the interrupt status register if bit gcr.vis is set after reset, all interrupts are dis abled. 70 imr0 rme rfs isf rmb rsc crc6 pden rpf (14) imr1 case rdo alls xdu xmb suex xlsc xpr (15) imr2 far lfa mfar lmfa ais los rar ra (16) imr3 es sec llbsc rsn rsp (17) imr4 xsp xsn rme2 rfs2 rdo2 alls2 xdu2 rpf2 (18) imr5 xpr2 xpr3 rme3 rfs3 rdo3 alls3 xdu3 rpf3 (19) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 360 ds1.1, 2003-10-23 hardware description single bit defect insertion register (read/write) value after reset: 00 h after setting the corresponding bit, the selected defect is inserted into the transmit data stream at the next possible position. after defect insertion is completed, the bit is reset automatically. ifase insert single fas defect imfe insert single multiframe defect icrce insert single crc defect icase insert single cas defect ipe insert single prbs defect ibv insert bipolar violation note: except for crc defects, crc checksum calculation is done after defect insertion. framer mode register 0 (read/write) value after reset: 00 h xc(1:0) transmit code serial line code for the transmitter, independent of the receiver. 00 = nrz (optical interface) 01 = cmi (1t2b+b8zs), (optical interface) 10 = ami coding with zero code suppression (zcs, b7-stuffing). disabling of the zcs is done by activating the clear channel mode by register ccb(3:1). (ternary or digital interface) 11 = b8zs code (ternary or digital dual-rail interface). after changing xc(1:0), a transmitter software reset is required (cmdr.xres = 1). rc(1:0) receive code serial code receiver is independent to the transmitter. ierr ifase imfe icrce icase ipe ibv (1b) 70 fmr0 xc1 xc0 rc1 rc0 frs sraf exls sim (1c) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 361 ds1.1, 2003-10-23 hardware description 00 = nrz (optical interface) 01 = cmi (1t2b+b8zs), (optical interface) 10 = ami coding with zero code suppression (zcs, b7-stuffing), (ternary or digital dual-rail interface) 11 = b8zs code (ternary or digital dual-rail interface) after changing rc(1:0), a receiver software reset is required (cmdr.rres = 1). frs force resynchronization a transition from low to high forces the frame aligner to execute a resynchronization of the pulse frame. in the asynchronous state, a new frame position is assumed at the next candidate if there is one. otherwise, a new frame search with the meaning of a general reset is started. in the synchronous state this bit has the same meaning as bit fmr0.exls except if fmr2.mcsp = 1. sraf select remote (yellow) alarm format for f12 and esf format 0 = f12: bit2 = 0 in every channel. esf: pattern ?1111 1111 0000 0000? in data link channel. 1 = f12: fs-bit of frame 12. esf: bit2 = 0 in every channel exls external loss of frame with a low to high transition a new frame search is started. this has the meaning of a general reset of the internal frame alignment unit. synchronous state is reached only if there is one definite framing candidate. in the case of multiple candidates, the setting of the bit fmr0.frs forces the receiver to lock onto the next available framing position. sim alarm simulation setting/resetting this bit initiates internal error simulation of: ais (blue alarm), loss-of-signal (red alarm), loss of frame alignment, remote (yellow) alarm, slip, framing errors, crc errors, code violations. the error counters fec, cvc, cec, ebc are incremented. the selection of simulated alarms is done by the error simulation counter: frs2.esc(2:0) which is incremented with each setting of bit fmr0.sim. for complete checking of the alarm indications eight simulation steps are necessary (frs2.esc(2:0) = 0 after a complete simulation). sim has to be held stable at high or low level for at least one receive clock period before changing it again. falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 362 ds1.1, 2003-10-23 hardware description framer mode register 1 (read/write) value after reset: 00 h ctm channel translation mode 0 = channel translation mode 0 1 = channel translation mode 1 the different channel translation modes are described in table 31 on page 135 . edl enable dl-bit access through register xdl(3:1) only applicable in f4, f24 or f72 frame format. 0 = normal operation. the dl-bits are taken from system highway or if enabled by ccr1.edlx from the xfifo of the signaling controller. 1 = dl-bit register access. the dl-bit information are taken from the registers xdl(3:1) and overwrite the dl-bits received on the system highway (pin xdi) or from the internal xfifo of the signaling controller. however, transmission of the contents of registers xdl(3:1) is disabled if transparent mode is enabled (fmr4.tm). pmod pcm mode for e1 application this bit must be set low. switching from e1 to t1 or vice versa the device needs up to 20 s to settle up to the internal clocking. 0 = pcm 30 or e1 mode. 1 = pcm 24 or t1/j1 mode (see rc0.sjr for t1/j1 selection). crc enable crc6 this bit is only significant when using the esf format. 0 = crc6 check/generation disabled. for transmit direction, all crc bit positions are set. 1 = crc6 check/generation enabled. 70 fmr1 ctm edl pmod crc ecm ssd0 xais (1d) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 363 ds1.1, 2003-10-23 hardware description ecm error counter mode the function of the error counters (fec,cec,cvc,ebc) is determined by this bit. 0 = before reading an error counter the corresponding bit in the disable error counter register (dec) has to be set. in 8 bit access the low byte of the error counter should always be read before the high byte. the error counters are reset with the rising edge of the corresponding bits in the dec register. 1 = every second the error counter is latched and then automatically reset. the latched error counter state should be read within the next second. reading the error counter during updating should be avoided (do not access an error counter within 1 s after the one-second interrupt occurs). ssd0 select system date rate 0 sic1.ssd1, fmr1.ssd0 and sic2.ssc2 define the data rate on the system highway. programming ssd1/ssd0 and corresponding data rate is shown below. sic2.ssc2 = 0: 00 = 2.048 mbit/s 01 = 4.096 mbit/s 10 = 8.192 mbit/s 11 = 16.384 mbit/s sic2.ssc2 = 1: 00 = 1.544 mbit/s 01 = 3.088 mbit/s 10 = 6.176 mbit/s 11 = 12.352 mbit/s xais transmit ais towards remote end sends ais (blue alarm) on ports xl1, xl2 towards the remote end. if local loop mode is enabled the transmitted data is looped back to the system internal highway without any changes. falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 364 ds1.1, 2003-10-23 hardware description framer mode register 2 (read/write) value after reset: 00 h afrs automatic force resynchronization 0 = default operation, no automatic search in case of multiple framing candidates. 1 = search for next framing candidate automatically, if multiple candidates are present and the current candidate is incorrect. mcsp multiple candidates synchronization procedure ssp select synchronization/resynchronization procedure together with bit fmr2.ssp the synchronization mode of the receive framer is defined: mcsp/ssp: 00 = f12/f72 format: specified number of errors in both ft framing and fs framing lead to loss of sync (frs0.lfa is set). in the case of fs-bit framing errors, bit frs0.lmfa is set additionally. a complete new synchronization procedure is initiated to regain pulseframe alignment and then multiframe alignment. f24: normal operation: synchronization is achieved only on verification the framing pattern. 01 = f12/f72: specified number of errors in ft framing has the same effect as above. specified number of errors in fs framing only initiates a new search for multiframe alignment without influencing pulseframe synchronous state (frs0.lmfa is set). f24: synchronous state is reached when three consecutive multiframe pattern are correctly found independent of the occurrence of crc6 errors. 10 = f12/f24: a one enables a synchronization mode which is able to choose multiple framing pattern candidates step by step. i.e. if in synchronous state the crc error counter indicates that the synchronization might 70 fmr2 afrs mcsp ssp dais sais plb axra exze (1e) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 365 ds1.1, 2003-10-23 hardware description have been based on an alias framing pattern, setting of fmr0.frs leads to synchronization on the next candidate available. however, only the previously assumed candidate is discarded in the internal framing pattern memory. the latter procedure can be repeated until the framer locks on the right pattern (no extensive crc errors). therefore bit fmr1.crc must be set. 11 = f24: synchronization is achieved on verification the framing pattern and the crc6 bits. synchronous state is reached when framing pattern and crc6 checksum are correctly found. for correct operation the crc check must be enabled by setting bit fmr1.crc. dais disable ais to system interface 0 = ais is automatically inserted into the data stream to rdo if falc ? 56 is in asynchronous state. 1 = automatic ais insertion is disabled. furthermore, ais insertion can be initiated by programming bit fmr2.sais. sais send ais towards system interface sends ais (blue alarm) on output rdo towards system interface. this function is not influenced by bit fmr2.dais. plb payload loop-back 0 = normal operation. payload loop is disabled. 1 = the payload loop-back loops the data stream from the receiver section back to transmitter section. looped data is output on pin rdo. data received on port xdi, xsig, sypx and xmfs is ignored. with fmr4.tm = 1 all 193 bits per frame are looped back. if fmr4.tm = 0 the dl- or fs- or crc-bits are generated internally. ais is sent immediately on port rdo by setting the fmr2.sais bit. during payload loop is active the receive time slot offset (registers rc(1:0)) should not be changed. it is recommended to write the actual value of xc1 into this register once again, because a write access to register xc1 sets the read/write pointer of the transmit elastic buffer into its optimal position to ensure a maximum wander compensation (the write operation forces a slip). axra automatic transmit remote alarm 0 = normal operation 1 = the remote alarm (yellow alarm) bit is set automatically in the outgoing data stream for the duration of the alarm but at least falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 366 ds1.1, 2003-10-23 hardware description one second according to ansi t1.403-1999 if the receiver is in asynchronous state (frs0.lfa bit is set). in synchronous state the remote alarm bit is reset. the minimum time between the end of one transmission of rai and the beginning of another transmission of rai is one second. the rai is transmitted in the following forms: - superframe format (f4, f12, f72): for the duration of the alarm condition but at least for one second bit two in every ds0 channel is a zero, even if the payload is not channelized. - esf: for the duration of the alarm condition but at least for one second a repeating 16-bit pattern consisting of eight ?ones? followed by eight ?zeros? is transmitted continuously on the esf data link, but may be interrupted for a period not to exceed 100 ms per interruption. exze excessive zeros detection enable selects error detection mode in the bipolar receive bit stream. 0 = only bipolar violations are detected. 1 = bipolar violations and zero strings of 8 or more contiguous zeros in b8zs code or more than 15 contiguous zeros in ami code are detected additionally and counted in the code violation counter (cvc). falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 367 ds1.1, 2003-10-23 hardware description loop (read/write) value after reset: 00 h rtm receive transparent mode setting this bit disconnects control of the internal elastic store from the receiver. the elastic store is now in a ?free running? mode without any possibility to actualize the time slot assignment to a new frame position in case of resynchronization of the receiver. this function can be used together with the ?disable ais to system interface? feature (fmr2.dais) to realize undisturbed transparent reception. this bit should be enabled in case of unframed data reception mode. eclb enable channel loop-back 0 = disables the channel loop-back. 1 = enables the channel loop-back selected by this register. note:cas-br must be switched off (fmr5.eibr = 0) while channel loop back is enabled. cla(4:0) channel address for loop-back cla = 1 to 24 selects the channel. during loop-back, the contents of the associated outgoing channel on ports xl1/xdop/xoid and xl2/xdon is equal to the idle channel code programmed in register idle. 70 loop rtm eclb cla4 cla3 cla2 cla1 cla0 (1f) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 368 ds1.1, 2003-10-23 hardware description framer mode register 4 (read/write) value after reset: 00 h ais3 select ais condition 0 = ais (blue alarm) is indicated (frs0.ais) when two or less zeros in the received bit stream are detected in a time interval of 12 frames (f4, f12, f72) or 24 frames (esf). 1 = ais (blue alarm) detection is only enabled when falc ? 56 is in asynchronous state. the alarm is indicated (frs0.ais) when ? three or less zeros within a time interval of 12 frames (f4, f12, f72), or ? five or less zeros within a time interval of 24 frames (esf) are detected in the received bit stream. tm transparent mode setting this bit enables the transparent mode: in transmit direction bit 8 of every fs/dl time slot from the system internal highway (xdi) is inserted in the f-bit position of the outgoing frame. internal framing generation, insertion of crc and dl data is disabled. xra transmit remote alarm (yellow alarm) if high, remote alarm is sent on the pcm route. clearing the bit removes the remote alarm pattern. remote alarm indication depends on the multiframe structure as follows: f4: bit2 = 0 in every speech channel f12: ? fmr0.sraf = 0: bit2 = 0 in every speech channel ? fmr0.sraf = 1: fs-bit of frame 12 is forced to ?1? esf: ? fmr0.sraf = 0: pattern ?1111111100000000 11111111000? in data link channel ? fmr0.sraf = 1: bit2 = 0 in every speech channel f72: bit2 = 0 in every speech channel 70 fmr4 ais3 tm xra ssc1 ssc0 auto fm1 fm0 (20) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 369 ds1.1, 2003-10-23 hardware description ssc(1:0) select sync conditions loss of frame alignment (frs0.lfa or opt. frs0.lmfa) is declared if: 00 = 2 out of 4 framing bits 01 = 2 out of 5 framing bits 10 = 2 out of 6 framing bits in f4/12/72 format 10 = 2 out of 6 framing bits per multiframe period in esf format 11 = 4 consecutive multiframe pattern in esf format are incorrect. it depends on the selected multiframe format and optionally on bit fmr2.ssp which framing bits are observed: f4: ft-bits frs0.lfa f12, f72: ssp = 0: ft-bits frs0.lfa fs-bits frs0.lfa and frs0.lmfa f12, f72: ssp = 1: ft frs0.lfa fs frs0.lmfa esf: esf framing bits frs0.lfa auto enable auto resynchronization 0 = the receiver does not re synchronize automatically. starting a new synchronization procedure is possible by the bits fmr0.exls or fmr0.frs. 1 = auto-resynchronization is enabled. fm(1:0) select frame mode fm = 0: 12-frame multiframe format (f12, d3/4) fm = 1: 4-frame multiframe format (f4) fm = 2: 24-frame multiframe format (esf) fm = 3: 72-frame multiframe format (f72, remote switch mode) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 370 ds1.1, 2003-10-23 hardware description framer mode register 5 (read/write) value after reset: 00 h eibr enable internal bit robbing access 0 = normal operation. 1 = a one in this bit position causes the transmitter to send the bit robbing signaling information stored in the xs(12:1) (esf, f12, 72) registers or serial cas in the corresponding time slots. xld transmit line loop-back (llb) down code 0 = normal operation. 1 = a one in this bit position causes the transmitter to replace normal transmit data with the llb down (deactivate) code continuously until this bit is reset. the llb down code is overwritten by the framing/dl/crc bits optionally. xlu transmit llb up code 0 = normal operation. 1 = a one in this bit position causes the transmitter to replace normal transmit data with the llb up (activate) code continuously until this bit is reset. the llb up code is optionally overwritten by the framing/dl/crc bits. for proper operation bit fmr5.xld must be cleared. xtm transmit transparent mode 0 =ports sypx /xmfs define the frame/multiframe begin on the transmit system highway. the transmitter is usually synchronized on this externally sourced frame boundary and generates the fs/dl-bits according to this framing. any change of the transmit time slot assignment subsequently produces a change of the fs/dl-bit positions. 1 = disconnects the control of the transmit system interface from the transmitter. the transmitter is now in a free running mode without any possibility to actualize the multiframe position. the framing (fs/dl-bits) generated by the transmitter are not ?disturbed? (in case of changing the transmit time slot assignment) by the transmit system highway unless register xc1 is written. this bit should be set if loop-timed application is 70 fmr5 eibr xld xlu xtm ssc2 (21) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 371 ds1.1, 2003-10-23 hardware description selected. for proper operation the transmit elastic buffer (2 frames, sic1.xbs(1:0) = 10) has to be enabled. ssc2 select sync conditions only valid in esf framing format. loss of frame alignment frs0.lfa is declared if more than 320 crc6 errors per second interval are detected. transmit control 0 (read/write) value after reset: 00 h brm enable bit robbing marker a one in this bit marks the robbed bit positions on the system highway. rsigm marks the receive and xsigm marks the transmit robbed bits. mfbs enable pure multiframe begin signals only valid if esf or f72 format is selected. 0 = rmfb marks the beginning of every received superframe. additional pulses are provided every 12 frames when using esf/f24 or f72 format. 1 = rmfb marks the beginning of every received multiframe. brfo(1:0) bit robbing force one cas-br information can be transferred to the system interface or be set to a fixed value. 00 = normal operation, robbed bits are transferred on rdo as they are received. 01 = robbed bits are forced high on rdo, even if marked as "cleared channels". 10 = reserved 11 = robbed bits are forced high on rdo except for those channels marked as "cleared"channels". xco(10:8) transmit offset initial value loaded into the transmit bit counter at the trigger edge of sclkx when the synchronous pulse on port sypx or xmfs is active refer to register xc1. 70 xc0 brm mfbs 0 brfo(1:0) xco10 xco9 xco8 (22) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 372 ds1.1, 2003-10-23 hardware description transmit control 1 (read/write) value after reset: 9c h a write access to this address resets the transmit elastic buffer to its basic starting position. therefore, updating the value should only be done when the falc ? 56 is initialized or when the buffer should be centered. as a consequence a transmit slip will occur. xco(7:0) transmit offset initial value loaded into the transmit bit counter at the trigger edge of sclkx when the synchronous pulse on port sypx /xmfs is active. calculation of delay time t (sclkx cycles) depends on the value x of the transmit offset register xc(1:0): system clocking rate: modulo 2.048 mhz (sic2.ssc2 = 0) 0 t 4: x = 4 - t 5 t maximum delay: x = 256 sc/sd - t + 4) with maximum delay = (256 sc/sd) -1 with sc = system clock defined by sic1.ssc(1:0)+sic2.ssc2 with sd = 2.048 mbit/s (system clocking n 2.048 mhz) or system clocking rate: modulo 1.544 mhz (sic2.ssc2 = 1) 0 t 4: x = 3 - t + 7 sc/bf 5 t maximum delay: x = 200 sc/bf - t + 3 with sc = system clock defined by sic1.ssc(1:0)+sic2.ssc2 sd = 1.544 mbit/s (system clocking n 1.544 mhz) with bf = basic frequency = 1.544 mhz t = time between the active edge of sclkx after sypx pulse begin and beginning of the next frame (f-bit, channel phase 0), measured in number of sclkx clock intervals; maximum delay: t max =(200 sc/bf)-(7 sc/bf)-1 see page 185 for further description. 70 xc1 xco7 xco0 (23) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 373 ds1.1, 2003-10-23 hardware description receive control 0 (read/write) value after reset: 00 h sjr select japanese itu-t requirements 0 = t1: alarm handling is done according itu-t g. 704+706 1 = j1: alarm handling is done according itu-t jg. 704+706 rram receive remote alarm mode the conditions for remote (yellow) alarm (frs0.rra) detection can be selected by this bit to allow detection even in the presence of a bit error rate of up to 10 -3 : rram = 0 detection f4: bit2 = 0 in every speech channel per frame. f12: ? fmr0.sraf = 0: bit2 = 0 in every speech channel per frame. ? fmr0.sraf = 1: s-bit of frame 12 is forced to ?1? esf: ? fmr0.sraf = 0: pattern ?1111 1111 0000 0000? in data link channel ? fmr0.sraf = 1: bit2 = 0 in every speech channel f72: bit2 = 0 in every speech channel per frame. release: the alarm is reset when above conditions are no longer detected. rram = 1 (bit error rate 10 -3 ) detection f4: bit2 = 0 in 255 consecutive speech channels. f12: ? fmr0.sraf = 0: bit 2 = 0 in 255 consecutive speech channels. ? fmr0.sraf = 1: s-bit of frame 12 is forced to ?1? esf: ? fmr0.sraf = 0: pattern ?1111 1111 0000 0000? in data link channel ? fmr0.sraf = 1: bit 2 = 0 in 255 consecutive speech channels f72: bit 2 = 0 in 255 consecutive speech channels. 70 rc0 sjr rram crci xcrci rdis rco10 rco9 rco8 (24) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 374 ds1.1, 2003-10-23 hardware description release depending on the selected multiframe format the alarm is reset when falc ? 56 does not detect ? the "bit 2 = 0" condition for three consecutive pulse frames (all formats if selected), ? the "fs-bit" condition for three consecutive multiframes (f12), ? the "dl pattern" for three times in a row (esf). crci automatic crc6 bit inversion if set, all crc bits of one outgoing extended multiframe are inverted in case a crc error is flagged for the previous received multiframe. this function is logica lly ored with rc0.xcrci. xcrci transmit crc6 bit inversion if set, the crc bits in the outgoing data stream are inverted before transmission. this function is logically ored with rc0.crci. rdis receive data input sense digital interface, dual-rail: 0 = inputs rdip/rdin are active low 1 = inputs rdip/rdin are active high digital interface, cmi: 0 = input roid is active high 1 = input roid is active low rco(10:8) receive offset/receive frame marker offset depending on the rp(a to d) pin function different offsets can be programmed. the sypr and the rfm pin function cannot be selected in parallel. receive offset (pc(4:1).rpc(2:0) = 000) initial value loaded into the receive bit counter at the trigger edge of sclkr when the synchronous pulse on port sypr is active. calculation of delay time t (sclkr cycles) depends on the value x of the receive offset register rc(1:0). refer to register rc1. falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 375 ds1.1, 2003-10-23 hardware description receive control 1 (read/write) value after reset: 9c h rco(7:0) receive offset/receive frame marker offset depending on the rp(a to d) pin function different offsets can be programmed. the sypr and the rfm pin function cannot be selected in parallel. receive offset (pc(4:1).rpc(2:0) = 000) initial value loaded into the receive bit counter at the trigger edge of sclkr when the synchronous pulse on port sypr is active. calculation of delay time t (sclkr cycles) depends on the value x of the receive offset register rc(1:0): system clocking rate: modulo 2.048 mhz (sic2.ssc2 = 0) 0 t 4:x = 4 - t 5 t maximum delay:x = 2052 - t with maximum delay = (256 sc/sd) -1 with sc = system clock defined by sic1.ssc(1:0)+sic2.ssc2 with sd = system data rate or system clocking rate: modulo 1.544 mhz (sic2.ssc2 = 1) 0 t 4:x = 4 - t + (7 sc/sd) 5 t maximum delay :x = (200 sc/sd) + 4 - t with maximum delay = 193 sc/sd - 1 with sc = system clock defined by sic1.ssc(1:0)+sic2.ssc2 with sd = system data rate delay time t = time between beginning of time slot 0 at rdo and the initial edge of sclkr after sypr goes active. see page 175 for further description. 70 rc1 rco7 rco5 rco0 (25) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 376 ds1.1, 2003-10-23 hardware description receive frame marker offset (pc(4:1).rpc(2:0) = 001 b ) offset programming of the receive frame marker which is output on multifunction port rfm. the receive frame marker can be activated during any bit position of the entire frame and depends on the selected system clock rate. calculation of the value x of the receive offset register rc(1:0) depends on the bit position which should be marked at marker position mp: system clocking rate: modulo 2.048 mhz (sic2.ssc2 = 0) 0 mp 2045:x = mp + 2 2046 mp 2047:x = mp - 2046) e.g: 2.048 mhz: mp = 0 to 255; 4.096 mhz: mp = 0 to 511, 8.192 mhz: mp = 0 to 1023, 16.384 mhz: mp = 0 to 2047 system clocking rate: modulo 1.544 mhz (sic2.ssc2 = 1) 0 mp 193 (sc/sd) - 3:x = mp + 2 + 7 sc/sd 193 (sc/sd) -2 mp maximum delay: x=mp+2-186 sc/sd with maximum delay = 193 sc/sd - 1 with sc = system clock defined by sic1.ssc(1:0)+sic2.ssc2 with sd = system data rate falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 377 ds1.1, 2003-10-23 hardware description transmit pulse-mask registers (read/write) value after reset: 7b h , 03 h , 40 h the transmit pulse shape which is defined in ansi t1.102 is output on pins xl1 and xl2. the level of the pulse shape can be programmed by registers xpm(2:0) to create a custom waveform. in order to get an optimized pulse shape for the external transformers each pulse shape is internally divided into four sub pulse shapes. in each sub pulse shape a programmed 5 bit value defines the level of the analog voltage on pins xl1/2. together four 5 bit values have to be programmed to form one complete transmit pulse shape.the four 5 bit values are sent in the following sequence: xp04 to 00: first pulse shape level xp14 to 10: second pulse shape level xp24 to 20: third pulse shape level xp34 to 30: fourth pulse shape level changing the lsb of each subpulse in registers xpm(2:0) changes the amplitude of the differential voltage on xl1/2 by approximately 90 mv. the xpm values in the following table are based on simulations. they are valid for the following external circuitry: transformer ratio 1:2.4, cable pulb 22awg (100 ? ), serial resistors 2 ? . adjustment of these coefficients can be necessary for other external conditions. 70 xpm0 xp12 xp11 xp10 xp04 xp03 xp02 xp01 xp00 (26) xpm1 xp30 xp24 xp23 xp22 xp21 xp20 xp14 xp13 (27) xpm2 0 xlt daxlt xp34 xp33 xp32 xp31 (28) table 68 pulse shaper programming (t1/j1) 1) 1) register values of v1.2 may also be used. for optimum results v2.1 values must be applied. range in m range in ft. xpm0 xpm1 xpm2 xp04- xp00 xp14- xp10 xp24- xp20 xp34- xp30 hexadecimal decimal 0 to 40 0 to 133 95 16 01 21 20 5 2 40 to 81 133 to 266 b6 9e 01 22 21 7 3 81 to 122 266 to 399 d9 26 01 25 22 9 2 122 to 162 399 to 533 fc 36 01 28 23 13 2 162 to 200 533 to 655 3f cb 01 31 28 18 3 falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 378 ds1.1, 2003-10-23 hardware description xlt transmit line tristate 0 = normal operation 1 = transmit line xl1/xl2 or xdop/xdon are switched into high-impedance state. if this bit is set the transmit line monitor status information is frozen (default value after hardware reset). daxlt disable automatic tristating of xl1/2 0 = normal operation. if a short is detected on pins xl1/2 the transmit line monitor sets the xl1/2 outputs into a high-impedance state. 1 = if a short is detected on pins xl1/2, the automatic setting of these pins into a high-impedance state (by the xl-monitor) is disabled. idle channel code register (read/write) value after reset: 00 h idl(7:0) idle channel code if channel loop-back is enabled by programming the register loop.eclb = 1, the contents of the assigned outgoing channel on ports xl1/xl2 or xdop/xdon is set equal to the idle channel code selected by this register. additionally, the specified pattern overwrites the contents of all channels of the outgoing pcm frame selected by the idle channel registers icb(3:1). idl7 is transmitted first. transmit dl-bit register 1-3 (read/write) value after reset: 00 h , 00 h , 00 h 70 idle idl7 idl0 (2b) 70 xdl1 xdl17 xdl16 xdl15 xdl14 xdl13 xdl12 xdl11 xdl10 (2c) xdl2 xdl27 xdl26 xdl25 xdl24 xdl23 xdl22 xdl21 xdl20 (2d) xdl3 xdl37 xdl36 xdl35 xdl34 xdl33 xdl32 xdl31 xdl30 (2e) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 379 ds1.1, 2003-10-23 hardware description xdl(3:1) transmit fs/dl-bit data the dl-bit register access is enabled by setting bits fmr1.edl = 1. with the transmit multiframe begin an interrupt isr1.xmb is generated and the contents of these registers xdl(3:1) is copied into a shadow register. the contents is subsequently sent out in the data stream of the next outgoing multiframe if no transparent mode is enabled. xdl10 is sent out first. in f4 frame format only xdl10 + xdl11 are transmitted. in f24 frame format xdl10 to 23 are shifted out. in f72 frame format xdl10 to 37 are transmitted. the transmit multiframe begin interrupt (xmb) requests that these registers should be serviced. if requests for new information are ignored, the current contents is repeated. clear channel register (read/write) value after reset: 00 h , 00 h , 00 h ch(24:1) channel selection bits 0 = normal operation. bit robbing information and zero code suppression (zcs, b7 stuffing) can change contents of the selected speech/data channel if assigned modes are enabled by bits fmr5.eibr and fmr0.xc(1:0). 1 = clear channel mode. contents of selected speech/data channel are not overwritten by internal or external bit robbing and zcs information. transmission of channel assigned signaling and control of pulse-density is applied by the user. 70 ccb1 ch1 ch2 ch3 ch4 ch5 ch6 ch7 ch8 (2f) ccb2 ch9 ch10 ch11 ch12 ch13 ch14 ch15 ch16 (30) ccb3 ch17 ch18 ch19 ch20 ch21 ch22 ch23 ch24 (31) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 380 ds1.1, 2003-10-23 hardware description idle channel register (read/write) value after reset: 00 h , 00 h , 00 h , 00 h ic(24:1) idle channel selection bits these bits define the channels (time slots) of the outgoing pcm frame to be altered. 0 = normal operation. 1 = idle channel mode. the contents of the selected channel is overwritten by the idle channel code defined by register idle. line interface mode 0 (read/write) value after reset: 00 h xfb transmit full bauded mode only applicable for dual-rail mode (bit lim1.drs = 1). 0 = output signals xdop/xdon are half bauded (normal operation). 1 = output signals xdop/xdon are full bauded. note: if cmi coding is selected (fmr0.xc(1:0) = 01) this bit has to be cleared. 70 icb1 ic1 ic2 ic3 ic4 ic5 ic6 ic7 ic8 (32) icb2 ic9 ic10ic11ic12ic13ic14ic15ic16 (33) icb3 ic17 ic18 ic19 ic20 ic21 ic22 ic23 ic24 (34) 70 lim0 xfb xdos 0 dcim 1 rlm ll mas (36) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 381 ds1.1, 2003-10-23 hardware description xdos transmit data out sense 0 = output signals xdop/xdon are active low. output xoid is active high (normal operation). 1 = output signals xdop/xdon are active high. output xoid is active low. note: if cmi coding is selected (fmr0.xc(1:0) = 01) this bit has to be cleared. the transmit frame marker xfm is independent of this bit. dcim digital clocking interface mode 0 = default t1/j1 data operation. 1 = selects synchronization interface mode. a 1.544-mhz receive clock signal must be applied on rl1/rl2. the transmit clock signal must be derived from the clock connected to sclkx (cmr1.dxss = 1). the recommended xpm programming values are: xpm0 = ef h , xpm1 = bd h , xpm2 = 07 h rlm receive line monitoring 0 = normal receiver mode 1 = receiver mode for receive line monitoring; the receiver sensitivity is increased to detect resistively attenuated signals of -20 db (short-haul mode only) ll local loop 0 = normal operation 1 = local loop active. the local loop-back mode disconnects the receive lines rl1/rl2 or rdip/rdin from the receiver. instead of the signals coming from the line the data provided by system interface is routed through the analog receiver back to the system interface. the unipolar bit stream is transmitted undisturbedly on the line. receiver and transmitter coding must be identical. operates in analog and digital line interface mode. in analog line interface mode data is transferred through the complete analog receiver. mas master mode 0 = slave mode 1 = master mode on. setting this bit the dco-r circuitry is frequency synchronized to the clock (1.544, 2.048 mhz or 8 khz, see ipc.ssyf, lim1.dcoc) supplied by sync. if this pin is connected to v ss or v dd (or left open and pulled up to v dd falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 382 ds1.1, 2003-10-23 hardware description internally) the dco-r circuitry is centered and no receive jitter attenuation is performed (only if 1.544 or 2.048 mhz clock is selected by resetting bit ipc.ssyf). the generated clocks are stable. falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 383 ds1.1, 2003-10-23 hardware description line interface mode 1 (read/write) value after reset: 00 h clos clear data in case of los 0 = normal receiver mode, receive data stream is transferred normally in long-haul mode 1 = in long-haul mode received data is cleared (driven low), as soon as los is detected ril(2:0) receive input threshold only valid if analog line interface is selected (lim1.drs = 0). ?no signal? is declared if the voltage between pins rl1 and rl2 drops below the limits programmed by bits ril(2:0) and the received data stream has no transition for a period defined in the pcd register. the threshold where ?no signal? is declared is programmable by the ril(2:0) bits. see the dc characteristics for detail. dcoc dco-r control 0 = 1.544 mhz reference clock for the dco-r circuitry provided on pin sync. 1 = 2.048 mhz reference clock for the dco-r circuitry provided on pin sync. note:if ipc.ssyf = 1, external reference clock frequency is 8.0 khz independent of dcoc. 70 lim1 clos ril2 ril1 ril0 dcoc jatt rl drs (37) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 384 ds1.1, 2003-10-23 hardware description jatt, rl remote loop transmit jitter attenuator 00 = normal operation. the remote loop transmit jitter attenuator is disabled. transmit data bypasses the remote loop jitter attenuator buffer. 01 = remote loop active without transmit jitter attenuator enabled. transmit data bypasses the remote loop jitter attenuator buffer. 10 = not assigned 11 = remote loop and remote loop jitter attenuator active. received data from pins rl1/2 or rdip/n or roid is sent "jitter-free" on ports xl1/2 or xdop/n or xoid. the de-jittered clock is generated by the dco-x circuitry. note:jatt is only used to define the jitter attenuation during remote loop operation. jitter attenuation during normal operation is not affected. drs dual-rail select 0 = the ternary interface is selected. multifunction ports rl1/2 and xl1/2 become analog in/outputs. 1 = the digital dual-rail interface is selected. received data is latched on multifunction ports rdip/rdin while transmit data is output on pins xdop/xdon. pulse count detection register (read/write) value after reset: 00 h pcd(7:0) pulse count detection a los alarm (red alarm) is detected if the incoming data stream has no transitions for a programmable number t consecutive pulse positions. the number t is programmable by the pcd register and can be calculated as follows: t=16 (n+1); with 0 n 255. the maximum time is: 256 16 648 ns = 2.65 ms. every detected pulse resets the internal pulse counter. the counter is clocked with the receive clock rclk. 70 pcd pcd7 pcd0 (38) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 385 ds1.1, 2003-10-23 hardware description pulse count recovery (read/write) value after reset: 00 h pcr(7:0) pulse count recovery a los alarm (red alarm) is cleared if a pulse-density is detected in the received bit stream. the number of pulses m which must occur in the predefined pcd time interval is programmable by the pcr register and can be calculated as follows: m = n+1; with 0 n 255. the time interval starts with the first detected pulse transition. with every received pulse a counter is incremented and the actual counter is compared to the contents of pcr register. if the pulse number reaches or exceeds the pcr value the los alarm is reset otherwise the alarm stays active. in this case the next detected pulse transition starts a new time interval. an additional loss-of-signal recovery condition is selected by register lim2.los1. 70 pcr pcr7 pcr0 (39) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 386 ds1.1, 2003-10-23 hardware description line interface mode 2 (read/write) value after reset: 20 h lbo(2:1) line build-out in long-haul applications a transmit filter can be optionally placed on the transmit path to attenuate the data on pins xl1/2. selecting the transmitter attenuation is possible in steps of 7.5 db at 772khz which is according to fcc68 and ansi t1.403. to meet the line build-out defined by ansi t1.403 registers xpm(2:0) should be programmed as follows (based on 2 ? transmit resistors): 00 = 0.0 db xpm(2:0): refer to table 68 on page 377 . 01 = 7.5 db xpm(2:0) = 00 h , 01 h , 8c h 10 = -15 db xpm(2:0) = 01 h , 11 h , 8c h 11 = -22.5 db xpm(2:0) = 00 h , 01 h , 07 h slt(1:0) receive slicer threshold 00 = the receive slicer generates a mark (digital one) if the voltage at rl1/2 exceeds 55% of the peak amplitude. 01 = the receive slicer generates a mark (digital one) if the voltage at rl1/2 exceeds 67% of the peak amplitude (may be used in some t1/j1 applications). 10 = the receive slicer generates a mark (digital one) if the voltage at rl1/2 exceeds 50% of the peak amplitude (default, recommended in t1/j1 mode). 11 = the receive slicer generates a mark (digital one) if the voltage at rl1/2 exceeds 45% of the peak amplitude. scf select corner frequency of dco-r setting this bit reduces the corner frequency of the dco-r circuit by the factor of ten to 0.6 hz. note: reducing the corner frequency of the dco-r circuitry increases the synchronization time before the frequencies are synchronized. note: lim2.scf is ignored, if cmr2.ecfar is set. 70 lim2 lbo2 lbo1 slt1 slt0 scf elt mpas los1 (3a) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 387 ds1.1, 2003-10-23 hardware description elt enable loop-timed 0 = normal operation 1 = transmit clock is generated from the clock supplied by mclk which is synchronized to the extracted receive route clock. in this configuration the transmit elastic buffer has to be enabled. refer to register fmr5.xtm. for correct operation of loop timed the remote loop (bit lim1.rl = 0) must be inactive and bit cmr1.dxss must be cleared. mpas multi-purpose analog switch this bit controls the analog switch between pins as1 and as2. 0 = switch is open. 1 = switch is closed. los1 loss-of-signal recovery condition 0 = the los alarm is cleared if the predefined pulse-density (register pcr) is detected during the time interval which is defined by register pcd. 1 = additionally to the recovery condition described above a los alarm is only cleared if the pulse-density is fulfilled and no more than 15 contiguous zeros are detected during the recovery interval (according to gr-499-core). loop code register 1 (read/write) value after reset: 00 h eprm enable pseudo-random binary sequence monitor 0 = pseudo-random binary sequence (prbs) monitor is disabled. 1 = prbs is enabled. setting this bit enables incrementing the bit error counter bec with each detected prbs bit error. with any change of state of the prbs internal synchronization status an interrupt isr3.llbsc is generated. the current status of the prbs synchronizer is indicated by bit frs1.llbad. 70 lcr1 eprm xprbs ldc1 ldc0 lac1 lac0 fllb llbp (3b) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 388 ds1.1, 2003-10-23 hardware description xprbs transmit pseudo-random binary sequence a one in this bit position enables transmission of a pseudo-random binary sequence to the remote end. depending on bit llbp the prbs is generated according to 2 15 -1 or 2 20 -1 (itu-t o. 151). ldc(1:0) length deactivate (down) code these bits defines the length of the llb deactivate code which is programmable in register lcr2. 00 = length: 5 bit 01 = length: 6 bit, 2 bit, 3 bit 10 = length: 7 bit 11 = length: 8 bit, 2 bit, 4bit lac(1:0) length activate (up) code these bits defines the length of the llb activate code which is programmable in register lcr3. 00 = length: 5 bit 01 = length: 6 bit, 2 bit, 3 bit 10 = length: 7 bit 11 = length: 8 bit, 2 bit, 4bit fllb framed line loop-back/invert prbs depending on bit lcr1.xprbs this bit enables different functions: lcr1.xprbs = 0: 0 = the line loop-back code is transmitted including framing bits. llb code overwrites the framing bits. 1 = the line loop-back code is transmitted in framed mode. llb code does not overwrite the framing bits. invert prbs lcr1.xprbs = 1: 0 = the generated prbs is transmitted not inverted. 1 = the prbs is transmitted inverted. llbp line loop-back pattern lcr1.xprbs = 0 0 = fixed line loop-back code according to ansi t1. 403. 1 = enable user-programmable line loop-back code by register lcr2/3. falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 389 ds1.1, 2003-10-23 hardware description lcr1.xprbs = 1 or lcr1.eprm = 1 0= 2 15 -1 1= 2 20 -1 loop code register 2 (read/write) value after reset: 00 h ldc(7:0) line loop-back deactivate code if enabled by bit fmr5.xld = 1 the llb deactivate code automatically repeats until the llb generator is stopped. transmit data is overwritten by the llb code. ldc0 is transmitted last. for correct operations bit lcr1.xprbs has to cleared. if lcr2 is changed while the previous deactivate code has been detected and is still received, bit frs1.llbdd will stay active until the incoming signal changes or a receiver reset is initiated (cmdr.rres = 1). loop code register 3 (read/write) value after reset: 00 h lac(7:0) line loop-back activate code if enabled by bit fmr5.xlu = 1 the llb activate code automatically repeats until the llb generator is stopped. transmit data is overwritten by the llb code. lac0 is transmitted last. for correct operations bit lcr1.xprbs has to cleared. if lcr3 is changed while the previous activate code has been detected and is still received, bit frs1.llbad will stay active until the incoming signal changes or a receiver reset is initiated (cmdr.rres = 1). 70 lcr2 ldc7 ldc0 (3c) 70 lcr3 lac7 lac0 (3d) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 390 ds1.1, 2003-10-23 hardware description system interface control 1 (read/write) value after reset: 00 h ssc(1:0) select system clock sic1.ssc(1:0) and sic2.ssc2 define the clocking rate on the system highway. sic2.ssc2 = 0: 00 = 2.048 mhz 01 = 4.096 mhz 10 = 8.192 mhz 11 = 16.384 mhz sic2.ssc2 = 1: 00 = 1.544 mhz 01 = 3.088 mhz 10 = 6.176 mhz 11 = 12.352 mhz ssd1 select system data rate 1 sic1.ssd1, fmr1.ssd0 and sic2.ssc2 define the data rate on the system highway. programming ssd1/ssd0 and corresponding data rate is shown below. sic2.ssc2 = 0: 00 = 2.048 mbit/s 01 = 4.096 mbit/s 10 = 8.192 mbit/s 11 = 16.384 mbit/s sic2 .ssc2 = 1: 00 =1.544 mbit/s 01 = 3.088 mbit/s 10 = 6.176 mbit/s 11 = 12.352 mbit/s 70 sic1 ssc1 ssd1 rbs1 rbs0 ssc0 bim xbs1 xbs0 (3e) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 391 ds1.1, 2003-10-23 hardware description rbs(1:0) receive buffer size 00 = buffer size: 2 frames 01 = buffer size: 1 frame 10 = buffer size: 96 bits 11 = bypass of receive elastic store bim bit interleaved mode only applicable if bit sic2.ssc2 is cleared. if sic2.ssc2 is set high, the bit interleaved mode is automatically performed. 0 = byte interleaved mode 1 = bit interleaved mode xbs(1:0) transmit buffer size 00 = bypass of transmit elastic store 01 = buffer size: 1 frame 10 = buffer size: 2 frames 11 = buffer size: 96 bits system interface control 2 (read/write) value after reset: 00 h ffs force freeze signaling setting this bit disables updating of the receive signaling buffer and current signaling information is frozen. after resetting this bit and receiving a complete superframe updating of the signaling buffer is started again. the freeze signaling status can also be generated automatically by detection of a loss-of-signal alarm or a loss of frame alignment or a receive slip (only if external register access through rsig is enabled). this automatic freeze signaling function is logically ored with this bit. the current internal freeze signaling status is output on pin rp(a to d) with selected pin function freeze (pc(4:1).rpc(2:0) = 110). additionally this status is also available in register sis.sfs. 70 sic2 ffs ssf crb ssc2 sics2 sics1 sics0 (3f) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 392 ds1.1, 2003-10-23 hardware description ssf serial signaling format only applicable if pin function rsig/xsig and sic3.ttrf = 0 is selected. 0 = bits 1 to 4 in all time slots except time slot 0 are cleared. 1 = bits 1 to 4 in all time slots except time slot 0 are set high. crb center receive elastic buffer only applicable if the time slot assigner is disabled (pc(4:1).rpc(2:0) = 001 b ), no external or internal synchronous pulse receive is generated. a transition from low to high forces a receive slip and the read pointer of the receive elastic buffer is centered. the delay through the buffer is set to one half of the current buffer size. it should be hold high for at least two 1.544 mhz periods before it is cleared. ssc2 select system clock this bit together with sic1.ssc1/0 enables the system interface to run with a clock of 1.544, 3.088, 6.176 or 12.352 mhz (ssc2 = 1) or 2.048, 4.096, 8.192 or 16.384 mhz (ssc2 = 0). see also register sic1.ssc1/0 on page 390 . sics(2:0) system interface channel select only applicable if the system clock rate is greater than 1.544 ? 2.048mhz. received data is transmitted on pin rdo/rsig or received on xdi ? xsig with the selected system data rate. if the data rate is greater than 1.544/2.048 mbit/s the data is output or sampled in half, a quarter or one eighth of the time slot. data is not repeated. the time while data is active during a 8 488/648 ns time slot is called a channel phase. rdo/rsig are cleared (driven to low level) while xdi ? xsig are ignored for the remaining time of the 8 488/648 ns or for the remaining channel phases. the channel phases are selectable with these bits. 000 = data active in channel phase 1, valid if system data rate is 16/8/4 or 12/6/3 mbit/s 001 = data active in channel phase 2, valid if data rate is 16/8/4 or 12/6/3 mbit/s 010 = data active in channel phase 3, valid if data rate is 16/8 or 12/6 mbit/s 011 = data active in channel phase 4, valid if data rate is 16/8 or 12/6 mbit/s falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 393 ds1.1, 2003-10-23 hardware description 100 = data active in channel phase 5, valid if data rate is 16 or 12 mbit/s 101 = data active in channel phase 6, valid if data rate is 16 or 12 mbit/s 110 = data active in channel phase 7, valid if data rate is 16 or 12 mbit/s 111 = data active in channel phase 8, valid if data rate is 16 or 12 mbit/s system interface control 3(read/write) value after reset: 00 h cmi select cmi precoding only valid if cmi code (fmr0.xc(1:0) = 01) is selected. this bit defines the cmi precoding and influences transmit and receive data. 0 = cmi with b8zs precoding 1 = cmi without b8zs precoding note:before local loop is closed, b8zs precoding has to be switched off. rtri rdo/rsig tri-state mode 0 during incative channel phases, rdo and rsig are switched to low output level. 1 during incative channel phases, rdo and rsig are switched into tri-state mode. fsct sec/fsc tri-state mode 0 normal operation. 1 sec/fsc output is switched into tri-state mode. resx rising edge synchronous pulse transmit depending on this bit all transmit system interface data and marker are clocked or sampled with the selected active edge. cmr2.ixsc = 0: 70 sic3 cmi rtri fsct resx resr ttrf daf (40) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 394 ds1.1, 2003-10-23 hardware description 0 latched with the first falling edge of the selected pcm highway clock. 1 latched with the first rising edge of the selected pcm highway clock. cmr2.ixsc = 1: value of resx bit has no impact on the selected edge of the pcm highway clock but value of resr bit is used as resx. example: if resr = 0, the rising edge of pcm highway clock is the selected one for sampling data on xdi and vice versa. resr rising edge synchronous pulse receive depending on this bit all receive system interface data and marker are clocked with the selected active edge. 0 = latched with the first falling edge of the selected pcm highway clock. 1 = latched with the first rising edge of the selected pcm highway clock. note: if bit cmr2.irsp is set, the behavior of signal rfm (if used) is inverse (1 = falling edge, 0 = rising edge) ttrf ttr register function (fractional t1/j1 access) setting this bit the function of the ttr(4:1) registers are changed. a one in each ttr register forces the xsigm marker high for the corresponding time slot and controls sampling of the time slots provided on pin xsig. xsig is selected by pc(4:1).xpc(3:0). daf disable automatic freeze 0 = signaling is automatically frozen if one of the following alarms occurred: loss-of-signal (frs0.los), loss-of-frame- alignment (frs0.lfa), or receive slips (isr3.rsp/n). 1 = automatic freezing of signaling data is disabled. updating of the signaling buffer is also done if one of the above described alarm conditions is active. however, updating of the signaling buffer is stopped if sic2.ffs is set. significant only if the serial signaling access is enabled. falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 395 ds1.1, 2003-10-23 hardware description clock mode register 1 (read/write) value after reset: 00 h rs(1:0) select rclk source these bits select the source of rclk. 00 = clock recovered from the line through the dpll drives rclk 01 = clock recovered from the line through the dpll drives rclk and in case of an active los alarm rclk pin is set high. 10 = clock recovered from the line is de-jittered by dco-r to drive a 2.048 mhz (sic2.ssc2 = 0) or 1.544 mhz (sic2.ssc2 = 1) clock on rclk. 11 = clock recovered from the line is de-jittered by dco-r to drive a 8.192 mhz (sic2.ssc2 = 0) or 6.176 mhz (sic2.ssc2 = 1) clock on rclk. dcs disable clock-switching in slave mode (lim0.mas = 0) the dco-r is synchronized on the recovered route clock. in case of los the dco-r switches automatically to the clock sourced by port sync. setting this bit automatic switching from rclk to sync is disabled. stf select tclk frequency only applicable if the pin function tclk port xp(a to d) is selected by pc(4:1).xpc(3:0) = 0011 b . data on xl1/2, xdop/n, xoid are clocked with tclk. 0 = 1.544 mhz 1 = 6.176 mhz dxja disable internal transmit jitter attenuation setting this bit disables the transmit jitter attenuation. reading the data out of the transmit elastic buffer and transmitting on xl1/2 (xdop/n/xoid) is done with the clock provided on pin tclk. in transmit elastic buffer bypass mode the transmit clock is taken from sclkx, independent of this bit. 70 cmr1 rs1 rs0 dcs stf dxja dxss (44) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 396 ds1.1, 2003-10-23 hardware description dxss dco-x synchronization clock source 0 = the dco-x circuitry synchronizes to the internal reference clock which is sourced by sclkx/r or rclk. since there are many reference clock opportunities the following internal prioritizing in descending order from left to right is realized: lim1.rl > cmr1.dxss > lim2.elt > current working clock of transmit system interface. if one of these bits is set the corresponding reference clock is taken. 1 = dco-x synchronizes to an external reference clock provided on pin xp(a to d) pin function tclk, if no remote loop is active. tclk is selected by pc(4:1).xpc(3:0) = 0011 b clock mode register 2 (read/write) value after reset: 00 h ecfax enable corner frequency adjustment for dco-x 0 = corner frequency adjustment is disabled. 1 = corner frequency adjustment is enabled, values are programmed in cmr3.cfax (see page 400 ). note:dco-x must be enabled. ecfar enable corner frequency adjustment for dco-r 0 = corner frequency adjustment is disabled. 1 = corner frequency adjustment is enabled, values are programmed in cmr3.cfar. lim2.scf is ignored (see page 400 ). note:dco-r must be enabled. dcoxc dco-x center-frequency enable 0 = the center function of the dco-x circuitry is disabled. 1 = the center function of the dco-x circuitry is enabled. dco-x centers to 1.544 mhz related to the master clock reference (mclk), if reference clock (e.g. sclkx) is missing. 70 cmr2 exfax ecfar dcoxc dcf irsp irsc ixsp ixsc (45) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 397 ds1.1, 2003-10-23 hardware description dcf dco-r center- frequency disabled 0 = the dco-r circuitry is frequency centered - in master mode if no 1.544 or 2.048 mhz reference clock on pin sync is provided or - in slave mode if a loss-of-signal occurs in combination with no 1.544 or 2.048 mhz clock on pin sync or - a gapped clock is provided on pin rclki and this clock is inactive or stopped. 1 = the center function of the dco-r circuitry is disabled. the generated clock (dco-r) is frequency frozen in that moment when no clock is available on pin sync or pin rclki. the dco-r circuitry starts synchronization as soon as a clock on pins sync or rclki appears. irsp internal receive system frame sync pulse 0 = the frame sync pulse for the receive system interface is sourced by sypr (if sypr is applied). if sypr is not applied, the frame sync pulse is derived from rdo output signal internally free running). the use of irsp = 0 is recommended. 1 = the frame sync pulse for the receive system interface is internally sourced by the dco-r circuitry. this internally generated frame sync signal can be output (active low) on multifunction ports rp(a to d) (rpc(2:0) = 001 b ). note: this is the only exception where the use of rfm and sypr is allowed at the same time. because only one set of offset registers (rc1/0) is available, programming is done by using the sypr calculation formula in the same way as for the external sypr pulse. bit irsc must be set for correct operation. irsc internal receive system clock 0 = the working clock for the receive system interface is sourced by sclkr of or in receive elastic buffer bypass mode from the corresponding extracted receive clock rclk. 1 = the working clock for the receive system interface is sourced internally by dco-r or in bypass mode by the extracted receive clock. sclkr is ignored. falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 398 ds1.1, 2003-10-23 hardware description ixsp internal transmit system frame sync pulse 0 = the frame sync pulse for the transmit system interface is sourced by sypx . 1 = the frame sync pulse for the transmit system interface is internally sourced by the dco-r circuitry. additionally, the external xmfs signal defines the transmit multiframe begin. xmfs is enabled or disabled by the multifunction port configuration. for correct operation bits cmr2.ixsc/irsc must be set. sypx is ignored. ixsc internal transmit system clock 0 = the working clock for the transmit system interface is sourced by sclkx. 1 = the working clock for the transmit system interface is sourced internally by the working clock of the receive system interface. sclkx is ignored. falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 399 ds1.1, 2003-10-23 hardware description global configuration register (read/write) value after reset: 00 h vis masked interrupts visible 0 = masked interrupt status bits are not visible in registers isr(5:0). 1 = masked interrupt status bits are visible in isr(5:0), but they are not visible in registers gis. sci status change interrupt 0 = interrupts are generated either on activation or deactivation of the internal interrupt source. 1 = the following interrupts are activated both on activation and deactivation of the internal interrupt source: isr2.los, isr2.ais and isr0.pden ses select external second timer 0 = internal second timer selected 1 = external second timer selected ecmc error counter mode cofa 0 = not defined; reserved for future applications. 1 = a change of frame or multiframe alignment cofa is detected since the last resynchronization. the events are accumulated in the cofa event counter coec.(1:0). multiframe periods received in the asynchronous state are accumulated in the cofa event counter coec.(7:2). an overflow of each counter is disabled. pd power down switches between power-up and power-down mode. 0= power up 1= power down all outputs are driven inactive, except the multifunction ports, which are weakly driven high by the internal pullup devices. 70 gcr vis sci ses ecmc pd (46) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 400 ds1.1, 2003-10-23 hardware description errored second mask (read/write) value after reset: ff h esm errored second mask this register functions as an additional mask register for the interrupt status bit errored second (isr3.es). a "1" in a bit position of esm deactivates the related second interrupt. clock mode register 3 (read/write) value after reset: 00 h disable error counter (write) value after reset: 00 h drbd disable receive buffer delay this bit has to be set before reading the register rbd. it is automatically reset if rbd has been read. dcoec disable cofa event counter dbec disable prbs bit error counter only valid if lcr1.eprm = 1 and fmr1.ecm are reset. 70 esm lfa fer cer ais los cve slip (47) 70 cmr3 cfax(3:0) cfar(3:0) (48) table 69 dco-r and dco-x corner frequency programing (t1/j1) cfax(3:0) dco-x corner frequency [hz] cfar(3:0) dco-r corner frequency [hz] 7 0.6 7 0.6 3 6.0 3 6.0 70 dec drbd dcoec dbec dcec debc dcvc dfec (60) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 401 ds1.1, 2003-10-23 hardware description dcec disable crc error counter debc disable errored block counter dcvc disable code violation counter dfec disable framing error counter these bits are only valid if fmr1.ecm is cleared. they have to be set before reading the error counters. they are reset automatically if the corresponding error counter high byte has been read. with the rising edge of these bits the error counters are latched and then cleared. note: error counters and receive buffer delay can be read 1 s after setting the according bit in bit dec. transmit signaling register (write) value after reset: not defined transmit signaling register 1 to 12 the transmit signaling register access is enabled by setting bit fmr5.eibr = 1. each register contains the bit robbing information for 8 ds0 channels. with the transmit cas empty interrupt isr1.case the contents of these registers is copied into a shadow register. the contents is subsequently sent out in the corresponding bit positions of the next outgoing multiframe. xs1.7 is sent out first in channel 1 frame 1 and xs12.0 is sent out last. the transmit cas empty interrupt isr1.case requests that these registers table 70 transmit signaling registers (t1/j1) 70 xs1 a1 b1 c1/a2 d1/b2 a2/a3 b2/b3 c2/a4 d2/b4 (70) xs2 a3/a5 b3/b5 c3/a6 d3/b6 a4/a7 b4/b7 c4/a8 d4/b8 (71) xs3 a5/a9 b5/b9 c5/a10 d5/b10 a6/a11 b6/b11 c6/a12 d6/b12 (72) xs4 a7/a13 b7/b13 c7/a14 d7/b14 a8/a15 b8/b15 c8/a16 d8/b16 (73) xs5 a9/a17 b9/b17 c9/a18 d9/b18 a10/a19 b10/b19 c10/a20 d10/b20 (74) xs6 a11/a21 b11/b21 c11/a22 d11/b22 a12/a23 b12/b23 c12/a24 d12/b24 (75) xs7 a13/a1 b13/b1 c13/a2 d13/b2 a14/a3 b14/b3 c14/a4 d14/b4 (76) xs8 a15/a5 b15/b5 c15/a6 d15/b6 a16/a7 b16/b7 c16/a8 d16/b8 (77) xs9 a17/a9 b17/b9 c17/a10 d17/b10 a18/a11 b18/b11 c18/a12 d18/b12 (78) xs10 a19/a13 b19/b13 c19/a14 d19/b14 a20/a15 b20/b15 c20/a16 d20/b16 (79) xs11 a21/a17 b21/b17 c21/a18 d21/b18 a22/a19 b22/b19 c22/a20 d22/b20 (7a) xs12 a23/a21 b23/b21 c23/a22 d23/b22 a24/a23 b24/b23 c24/a24 d24/b24 (7b) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 402 ds1.1, 2003-10-23 hardware description should be serviced within the next 3 ms. if requests for new information are ignored, current contents is repeated. note: if access to xs(12:1) registers is done without control of the interrupt isr1.case and the write access to these registers is done exact in that moment when this interrupt is generated, data is lost. a software reset (cmdr.xres) resets these registers. port configuration 1 to 4 (read/write) value after reset: 00 h rpc(3:0) receive multifunction port configuration the multifunction ports rp(a to d) are bidirectional. after reset these ports are configured as inputs. with the selection of the pin function the in/output configuration is also achieved. the input function sypr may only be selected once, it must not be selected twice or more. register pc1 configures port rpa, while pc2 port rpb, pc3 port rpc and pc4 port rpd. 0000 = sypr : synchronous pulse receive (input) together with register rc(1:0) sypr defines the frame begin on the receive system interface. because of the offset programming the sypr and the rfm pin function cannot be selected in parallel. 0001 = rfm: receive frame marker (output) cmr2.irsp = 0 and gpc1.srfm = 0: the receive frame marker is active high for one 1.544 mhz period during any bit position of the current frame. programming of the bit position is done by using registers rc(1:0). the internal time slot assigner is disabled. the rfm offset calculation formula has to be used. cmr2.irsp = 0 and gpc1.srfm = 1: the receive frame marker is active high for one system period as programmed by sic1.ssc and sic2.ssc2 during any bit 70 pc1 rpc13 rpc12 rpc11 rpc10 xpc13 xpc12 xpc11 xpc10 (80) pc2 rpc23 rpc22 rpc21 rpc20 xpc23 xpc22 xpc21 xpc20 (81) pc3 rpc33 rpc32 rpc31 rpc30 xpc33 xpc32 xpc31 xpc30 (82) pc4 rpc43 rpc42 rpc41 rpc40 xpc43 xpc42 xpc41 xpc40 (83) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 403 ds1.1, 2003-10-23 hardware description position of the current frame. programming of the bit position is done by using registers rc(1:0). the internal time slot assigner is disabled. the rfm offset calculation formula has to be used. cmr2.irsp = 1: internally generated frame synchronization pulse sourced by the dco-r circuitry. the pulse is active low for one 1.544 mhz period. 0010 = rmfb: receive multiframe begin (output) marks the beginning of every received multiframe or optionally the begin of every cas multiframe begin (active high). 0011 = rsigm: receive signaling marker (output) marks the time slots which are defined by register rtr(4:1) of every frame on port rdo. 0100 = rsig: receive signaling data (output) the received cas multiframe is transmitted on this pin. time slot on rsig correlates directly to the time slot assignment on rdo. 0101 = dlr: data link bit receive (output) marks the s a -bits within the data stream on rdo. 0110 = freeze: freeze signaling (output) the freeze signaling status is active high by detecting a loss-of-signal alarm, or a loss of cas frame alignment or a receive slip (positive or negative). it stays high for at least one complete multiframe after the alarm disappears. setting sic2.ffs enforces a high on pin freeze. 0111 = rfsp : receive frame synchronous pulse (output) marks the frame begin in the receivers synchronous state. this marker is active low for 648 ns with a frequency of 8 khz. 1001 = gpi: general purpose input 1010 = gpoh: general purpose output high 1011 = gpol: general purpose output low 1100 = los: loss of signal output (status of frs0.los) xpc(3:0) transmit multifunction port configuration the multifunction ports xp(a to d) are bidirectional. after reset these ports are configured as inputs. with the selection of the pin function the in/output configuration is also achieved. each of the four different input functions (sypx , xmfs, xsig, tclk) may only be selected once. no input function must be selected twice or more. sypx and falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 404 ds1.1, 2003-10-23 hardware description xmfs should not be selected in parallel. register pc1 configures port xpa, while pc2 port xpb, pc3 port xpc and pc4 port xpd. 0000 = sypx : synchronous pulse transmit (input) together with register xc(1:0) sypx defines the frame begin on the transmit system interface ports xdi and xsig. 0001 = xmfs: transmit multiframe synchronization (input) together with register xc(1:0) xmfs defines the frame and multiframe begin on the transmit system interface ports xdi and xsig. depending on pc5.cxmfs the signal on xmfs is active high or low. 0010 = xsig: transmit signaling data (input) input for transmit signaling data received from the signaling highway. optionally sampling of xsig data is controlled by the active high xsigm marker. 0011 = tclk: transmit clock (input) a 1.544/6.176mhz clock has to be sourced by the system if the internal generated transmit clock (dco-x) is not used. optionally this input is used as a synchronization clock for the dco-x circuitry with a frequency of 1.544 or 6.176 mhz. 0100 = xmfb: transmit multiframe begin (output) marks the beginning of every transmit multiframe. 0101 = xsigm: transmit signaling marker (output) marks the time slots which are defined by register ttr(4:1) of every frame on port xdi. 0110 = dlx: data link bit transmit (output) marks the s a -bits within the data stream on xdi. 0111 = xclk: transmit line clock (output) frequency: 1.544mhz 1000 = xlt: transmit line tristate (input) with a high level on this port the transmit lines xl1/2 or xdop/n are set directly into tristate. this pin function is logically ored with register xpm2.xlt. 1001 = gpi: general purpose input 1010 = gpoh: general purpose output high 1011 = gpol: general purpose output low falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 405 ds1.1, 2003-10-23 hardware description port configuration 5 (read/write) value after reset: 00 h phdsx phase decoder switch for dco-x 0 = switch phase decoder divider by 1/3 (must be selected if dco-x is swiched off) 1 = switch phase decoder divider by 1/6 (slower adaption speed) phdsr phase decoder switch for dco-r 0 = switch phase decoder divider by 1/3 1 = switch phase decoder divider by 1/6 (slower adaption speed) cclk2 configure clk2 port 0 = clk2 is input 1 = clk2 is output (only if dco-x is active) cclk1 configure clk1 port 0 = clk1 is input 1 = clk1 is output (only if dco-r is active) cxmfs configure xmfs port 0 = port xmfs is active low. 1 = port xmfs is active high. csrp configure sclkr port 0 = sclkr: input 1 = sclkr: output crp configure rclk port 0 = rclk: input 1 = rclk: output 70 pc5 phdsx phdsr cclk2 cclk1 cxmfs 0 csrp crp (84) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 406 ds1.1, 2003-10-23 hardware description global port configuration 1 (read/write) value after reset: 00 h csfp(1:0) configure sec/fsc port the fsc pulse is generated if the dco-r circuitry of the selected channel is active (cmr2.irsc = 1 or cmr1.rs(1:0) = 10 b or 11 b ). sec/fsc can be switched into tristate mode by setting sic3.fsct. 00 = sec: input, active high 01 = sec: output, active high 10 = fsc: output, active high 11 = fsc: output, active low srfm set rfm according to system clock 0 = outgoing rfm on pin rpx is active high for 648 ns independent of the programmed system clock frequency. 1 = outgoing rfm on pin rpx is active high for one system clock period as programmed by sic.ssc and sic2.ssc2. note:only valid if corresponding pcx.rpc = 0001 b and cmr2.irsp = 0. 70 gpc1 csfp1 csfp0 srfm (85) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 407 ds1.1, 2003-10-23 hardware description port configuration 6 (read/write) value after reset: 00 h sxcl(1:0) select transmit clock frequency on port clk2 port clk2 is the de-jittered dco-x clock at a frequency of 00 = 1.544 mhz 01 = 3.088mhz 10 = 6.176 mhz 11 = 12.352 mhz note: if dco-x is not used, no clock is output on pin clk2 (sic1.xbs(1:0)=00 and cmr1.dxja=1; buffer bypass and no jitter attenuation) scl(2:0) select system clock frequency on port clk1 port clk1 is the de-jittered dco-r clock at a frequency of sic2.ssc2=0: 000 = 8 khz 001 = 2.048 mhz 010 = 4.096 mhz 011 = 8.192 mhz 100 = 16.384 mhz 101 to 111 = not defined sic2.ssc2=1: 000 = 8 khz 001 = 1.544 mhz 010 = 3.088 mhz 011 = 6.176 mhz 100 = 12.352 mhz 101 to 111 = not defined note: if dco-r is not active, no clock is output on pin clk1 (sic1.rbs(1:0)=11 and cmr1.rs1=0). 70 pc6 sxcl1 sxcl0 scl2 scl1 scl0 (86) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 408 ds1.1, 2003-10-23 hardware description command register 2 (write) value after reset: 00 h rsuc reset signaling unit counter - hdlc channel 1 after setting this bit the ss7 signaling unit counter and error counter are reset.the bit is cleared automatically after execution. note: the maximum time between writing to the cmdr2 register and the execution of the command takes 2.5 periods of the current system data rate. therefore, if the cpu operates with a very high clock rate in comparison with the falc ? 56's clock, it is recommended that bit sis.cec should be checked before writing to the cmdr register to avoid any loss of commands. xppr transmit periodical performance report (ppr) after setting this bit the last ppr is sent once. the bit is cleared automatically after completion. applies to hdlc channel 1 only. command register 3 (write) value after reset: 00 h rmc2 receive message complete - hdlc channel 2 confirmation from cpu to falc ? that the current frame or data block has been fetched following an rpf2 or rme2 interrupt, thus the occupied space in the rfifo2 can be released. xrep2 transmission repeat - hdlc channel 2 if xrep2 is set together with xtf2 (write 24h to cmdr3), the falc ? repeatedly transmits the contents of the xfifo2 (1 to 32 bytes) without hdlc framing fully transparently, i.e. without flag, crc. the cyclic transmission is stopped with an sres2 command or by resetting xrep2. cmdr2 rsuc xppr (87) 70 cmdr3 rmc2 xrep2 xhf2 xtf2 xme2 sres2 (88) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 409 ds1.1, 2003-10-23 hardware description xhf2 transmit hdlc frame - hdlc channel 2 after having written up to 32 bytes to the xfifo2, this command initiates the transmission of a hdlc frame. xtf2 transmit transparent frame - hdlc channel 2 initiates the transmission of a transparent frame without hdlc framing. xme2 transmit message end - hdlc channel 2 indicates that the data block written last to the xfifo2 completes the current frame. the falc ? can terminate the transmission operation properly by appending the crc and the closing flag sequence to the data. sres2 signaling transmitter reset - hdlc channel 2 the transmitter of the signaling controller is reset. xfifo2 is cleared of any data and an abort sequence (seven 1s) followed by interframe time fill is transmitted. in response to sres2 an xpr2 interrupt is generated. this command can be used by the cpu to abort a frame currently in transmission. command register 4 (write) value after reset: 00 h rmc3 receive message complete - hdlc channel 3 confirmation from cpu to falc ? that the current frame or data block has been fetched following an rpf3 or rme3 interrupt, thus the occupied space in the rfifo3 can be released. xrep3 transmission repeat - hdlc channel 3 if xrep3 is set together with xtf3 (write 24h to cmdr4), the falc ? repeatedly transmits the contents of the xfifo3 (1 to 32 bytes) without hdlc framing fully transparently, i.e. without flag, crc. the cyclic transmission is stopped with an sres3 command or by resetting xrep3. 70 cmdr4 rmc3 xrep3 xhf3 xtf3 xme3 sres3 (89) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 410 ds1.1, 2003-10-23 hardware description xhf3 transmit hdlc frame - hdlc channel 3 after having written up to 32 bytes to the xfifo3, this command initiates the transmission of a hdlc frame. xtf3 transmit transparent frame - hdlc channel 3 initiates the transmission of a transparent frame without hdlc framing. xme3 transmit message end - hdlc channel 3 indicates that the data block written last to the xfifo3 completes the current frame. the falc ? can terminate the transmission operation properly by appending the crc and the closing flag sequence to the data. sres3 signaling transmitter reset - hdlc channel 3 the transmitter of the signaling controller is reset. xfifo3 is cleared of any data and an abort sequence (seven 1s) followed by interframe time fill is transmitted. in response to sres3 an xpr3 interrupt is generated. this command can be used by the cpu to abort a frame currently in transmission. common configuration register 3 (read/write) value after reset: 00 h radd2 receive address pushed to rfifo2 if this bit is set, the received hdlc channel 2 address information (1 or 2 bytes, depending on the address mode selected via mode2.mds02) is pushed to rfifo2. this function is applicable in non-auto mode and transparent mode 1. 70 ccr3 radd2 rcrc2 xcrc2 itf2 xmfa2 rft12 rft02 (8b) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 411 ds1.1, 2003-10-23 hardware description rcrc2 receive crc on/off - hdlc channel 2 only applicable in non-auto mode. if this bit is set, the received crc checksum is written to rfifo2 (crc-itu-t: 2 bytes). the checksum, consisting of the 2 last bytes in the received frame, is followed in the rfifo2 by the status information byte (contents of register rsis2). the received crc checksum will additionally be checked for correctness. if non-auto mode is selected, the limits for ?valid frame? check are modified. xcrc2 transmit crc on/off - hdlc channel 2 if this bit is set, the crc checksum will not be generated internally. it has to be written as the last two bytes in the transmit fifo (xfifo2). the transmitted frame is closed automatically with a closing flag. itf2 interframe time fill - hdlc channel 2 determines the idle (= no data to be sent) state of the transmit data coming from the signaling controller. 0 = continuous logical "1" is output 1 = continuous flag sequences are output ("01111110" bit patterns) xmfa2 transmit multiframe aligned - hdlc channel 2 determines the synchronization between the framer and the corresponding signaling controller. 0 = the contents of the xfifo2 is transmitted without multiframe alignment. 1 = the contents of the xfifo2 is transmitted multiframe aligned. rft12, rft02 rfifo2 threshold level - hdlc channel 2 the size of the accessible part of rfifo2 can be determined by programming these bits. the number of valid bytes after an rpf interrupt is given in the following table: the value of rft(1:0)2 can be changed dynamically if reception is not running or after the current data block has been read, but before the command cmdr3.rmc2 is issued (interrupt controlled data transfer). rft12 rft02 size of accessible part of rfifo2 0 0 1 1 0 1 0 1 32 bytes (default value) 16 bytes 4 bytes 2 bytes falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 412 ds1.1, 2003-10-23 hardware description common configuration register 4 (read/write) value after reset: 00 h radd3 receive address pushed to rfifo3 if this bit is set, the received hdlc channel 3 address information (1 or 2 bytes, depending on the address mode selected via mode3.mds03) is pushed to rfifo3. this function is applicable in non-auto mode and transparent mode 1. rcrc3 receive crc on/off - hdlc channel 3 only applicable in non-auto mode. if this bit is set, the received crc checksum is written to rfifo3 (crc-itu-t: 2 bytes). the checksum, consisting of the 2 last bytes in the received frame, is followed in the rfifo3 by the status information byte (contents of register rsis3). the received crc checksum will additionally be checked for correctness. if non-auto mode is selected, the limits for ?valid frame? check are modified. xcrc3 transmit crc on/off - hdlc channel 3 if this bit is set, the crc checksum will not be generated internally. it has to be written as the last two bytes in the transmit fifo (xfifo3). the transmitted frame is closed automatically with a closing flag. itf3 interframe time fill - hdlc channel 3 determines the idle (= no data to be sent) state of the transmit data coming from the signaling controller. 0 = continuous logical "1" is output 1 = continuous flag sequences are output ("01111110" bit patterns) xmfa3 transmit multiframe aligned - hdlc channel 3 determines the synchronization between the framer and the corresponding signaling controller. 0 = the contents of the xfifo3 is transmitted without multiframe alignment. 1 = the contents of the xfifo3 is transmitted multiframe aligned. 70 ccr4 radd3 rcrc3 xcrc3 itf3 xmfa3 rft13 rft03 (8c) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 413 ds1.1, 2003-10-23 hardware description rft13, rft03 rfifo3 threshold level - hdlc channel 3 the size of the accessible part of rfifo3 can be determined by programming these bits. the number of valid bytes after an rpf interrupt is given in the following table: the value of rft13/03 can be changed dynamically if reception is not running or after the current data block has been read, but before the command cmdr4.rmc3 is issued (interrupt controlled data transfer). common configuration register 5 (read/write) value after reset: 00 h note:suet, csf and afx are only valid, if ss7 mode is selected. cr and epr are only valid, if ppr mode is selected. csf2 compare status field - mode 2 0 = compare disabled, if consecutive fisus are equal, only the first is stored and all following are ignored. 1 = compare enabled, if consecutive fisus are equal, the first two are stored and all following are ignored (according to itu-t q.703). suet signaling unit error threshold - hdlc channel 1 defines the number of signaling units received in error that will cause an error rate high indication (isr1.suex). 0 = threshold 64 errored signaling units 1 = threshold 32 errored signaling units rft13 rft03 size of accessible part of rfifo3 0 0 1 1 0 1 0 1 32 bytes (default value) 16 bytes 4 bytes 2 bytes 70 ccr5 csf2 suet csf afx cr epr (8d) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 414 ds1.1, 2003-10-23 hardware description csf compare status field - hdlc channel 1 if the status fields of consecutive lssus are equal, only the first is stored and every following is ignored. 0 = compare disabled. 1 = compare enabled. afx automatic fisu transmission - hdlc channel 1 after the contents of the transmit fifo (xfifo) has been transmitted completely, fisus are transmitted automatically. these fisus contain the fsn and bso of the last transmitted signaling unit (provided in xfifo). 0 = automatic fisu transmission disabled. 1 = automatic fisu transmission enabled. cr command response - hdlc channel 1 reflects the status of the cr bit in the sapi octet transmitted during periodical performance report (ppr), if ccr5.epr = 1. 0= cr bit=0 1= cr bit=1 epr enable periodical performance report (ppr) - hdlc channel 1 if the periodical performance report is to be used, an hdlc format must be selected by mode.mds(2:0). 0 = ppr disabled. 1 = ppr enabled. mode register 2 (read/write) value after reset: 00 h mds2(2:0) mode select - hdlc channel 2 the operating mode of the hdlc controller is selected. 000 = reserved 001 = reserved 010 = one-byte address comparison mode (ral1, 2) 011 = two-byte address comparison mode (rah1, 2 and ral1, 2) 70 mode2 mds22 mds21 mds20 hrac2 div2 (8e) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 415 ds1.1, 2003-10-23 hardware description 100 = no address comparison 101 = one-byte address comparison mode (rah1, 2) 110 = reserved 111 = no hdlc framing mode 1 hrac2 receiver active - hdlc channel 2 switches the hdlc receiver to operational or inoperational state. 0 = receiver inactive 1 = receiver active div2 data inversion - hdlc channel 2 setting this bit will invert the internal generated hdlc data stream. 0 = normal operation, hdlc data stream not inverted 1 = hdlc data stream inverted mode register 3 (read/write) value after reset: 00 h mds3(2:0) mode select - hdlc channel 3 the operating mode of the hdlc controller is selected. 000 = reserved 001 = reserved 010 = one-byte address comparison mode (ral1, 2) 011 = two-byte address comparison mode (rah1, 2 and ral1, 2) 100 = no address comparison 101 = one-byte address comparison mode (rah1, 2) 110 = reserved 111 = no hdlc framing mode 1 hrac3 receiver active - hdlc channel 3 switches the hdlc receiver to operational or inoperational state. 0 = receiver inactive 1 = receiver active 70 mode3 mds32 mds31 mds30 hrac3 div3 (8f) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 416 ds1.1, 2003-10-23 hardware description div3 data inversion - hdlc channel 3 setting this bit will invert the internal generated hdlc data stream. 0 = normal operation, hdlc data stream not inverted 1 = hdlc data stream inverted global clock mode register 1 (read/write) value after reset: 00 h see table 71 for programming. global clock mode register 2 (read/write) value after reset: 00 h see table 71 for programming. global clock mode register 3 (read/write) value after reset: 00 h see table 71 for programming. global clock mode register 4 (read/write) value after reset: 00 h see table 71 for programming. 70 gcm1 gcm1(7:0) (92) 70 gcm2 gcm2(7:0 (93) 70 gcm3 gcm3(7:0) (94) 70 gcm4 gcm4(7:0) (95) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 417 ds1.1, 2003-10-23 hardware description global clock mode register 5 (read/write) value after reset: 00 h see table 71 for programming. global clock mode register 6 (read/write) value after reset: 00 h see table 71 for programming. global clock mode register 7 (read/write) value after reset: 00 h see table 71 for programming. global clock mode register 8 (read/write) value after reset: 00 h see table 71 for programming. 70 gcm5 gcm5(7:0) (96) 70 gcm6 gcm6(7:0) (97) 70 gcm7 gcm7(7:0) (98) 70 gcm8 gcm8(7:0) (99) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 418 ds1.1, 2003-10-23 hardware description transmit fifo 2 (write) value after reset: 00 h xf(15:0) transmit fifo - hdlc channel 2 the function is equivalent to xfifo. transmit fifo 3 (write) value after reset: 00 h xf(15:0) transmit fifo - hdlc channel 3 the function is equivalent to xfifo. table 71 gcmx register programming line frequency [mhz] mclk [mhz] register settings 1) 1) xx = don?t care gcm1 gcm2 gcm3 gcm4 gcm5 gcm6 gcm7 gcm8 1.544 1.544 00 h 0d h 00 h 00 h 00 h 3f h 8c h 80 h 2.048 00 h 0c h 10 h 0c h 00 h 30 h 9c h 90 h 8.192 66 h 0e h 3f h 0f h 04 h 3c h 9c h 90 h 10.000 10 h 0e h cc h 0e h 05 h 3b h 9c h 90 h 12.352 a9 h 02 h 49 h 02 h 06 h 38 h ac h a0 h 16.384 49 h 02 h ca h 09 h 06 h 2a h ac h 90 h 19.440 32 h 0e h fa h 0e h 06 h 23 h 9c h 90 h 70 xfifo2 xf7 xf0 (9c) xfifo2 xf15 xf8 (9d) 70 xfifo3 xf7 xf0 (9e) xfifo3 xf15 xf8 (9f) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 419 ds1.1, 2003-10-23 hardware description time slot even/odd select (read/write) value after reset: 00 h hdlc protocol data can be sent in even, odd or both frames of a multiframe. even frames are frame number 2, 4, and so on, odd frames are frame number 1, 3, and so on. the selection refers to receive and transmit direction as well. each multiframe starts with an odd frame and ends with an even frame. by default all frames are used for hdlc reception and transmission. note: the different hdlc channels have to be configured to use different time slots, bit positions or frames. eo1(1:0) even/odd frame selection - hdlc channel 1 channel 1 hdlc protocol data can be sent in even, odd or both frames of a multiframe. 00 = even and odd frames 01 = odd frames only 10 = even frames only 11 = undefined eo2(1:0) even/odd frame selection - hdlc channel 2 channel 2 hdlc protocol data can be sent in even, odd or both frames of a multiframe. 00 = even and odd frames 01 = odd frames only 10 = even frames only 11 = undefined eo3(1:0) even/odd frame selection - hdlc channel 3 channel 3 hdlc protocol data can be sent in even, odd or both frames of a multiframe. 00 = even and odd frames 01 = odd frames only 10 = even frames only 11 = undefined 70 tseo eo31 eo30 eo21 eo20 eo11 eo10 (a0) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 420 ds1.1, 2003-10-23 hardware description time slot bit select 1 (read/write) value after reset: ff h tsb1(7:0) = time slot bit selection - hdlc channel 1 only bits selected by this register are used for hdlc channel 1 in selected time slots. time slot selection is done by setting the appropriate bits in registers ttr(4:1) and rtr(4:1) independently for receive and transmit direction. bit selection is common to receive and transmit direction. by default all bit positions within the selected time slot(s) are enabled. tsb1x = 0 to bit position x in selected time slot(s) is not used for hdlc channel 1 reception and transmission. tsb1x = 1 to bit position x in selected time slot(s) is used for hdlc channel 1 reception and transmission. time slot bit select 2 (read/write) value after reset: ff h tsb2(7:0) time slot bit selection - hdlc channel 2 only bits selected by this register are used for hdlc channel 2 in selected time slots. time slot selection is done by setting the appropriate bits in register tss2. bit selection is common to receive and transmit direction. by default all bit positions within the selected time slot are enabled. tsb2x=0 to bit position x in selected time slot(s) is not used for hdlc channel 2 reception and transmission. tsb2x=1 to bit position x in selected time slot(s) is used for hdlc channel 2 reception and transmission. 70 tsbs1 tsb17 tsb16 tsb15 tsb14 tsb13 tsb12 tsb11 tsb10 (a1) 70 tsbs2 tsb27 tsb26 tsb25 tsb24 tsb23 tsb22 tsb21 tsb20 (a2) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 421 ds1.1, 2003-10-23 hardware description time slot bit select 3 (read/write) value after reset: ff h tsb3(7:0) time slot bit selection - hdlc channel 3 only bits selected by this register are used for hdlc channel 3 in selected time slots. time slot selection is done by setting the appropriate bits in register tss3. bit selection is common to receive and transmit direction. by default all bit positions within the selected time slot are enabled. tsb3x=0 to bit position x in selected time slot(s) is not used for hdlc channel 3 reception and transmission. tsb3x=1 to bit position x in selected time slot(s) is used for hdlc channel 3 reception and transmission. time slot select 2 (read/write) value after reset: 00 h tss2(4:0) time slot selection code - hdlc channel 2 defines the time slot used by hdlc channel 2. 00000 =no time slot selected 00001 =time slot 1 ... 11111 =time slot 31 note: different hdlc channels must use different time slots. 70 tsbs3 tsb37 tsb36 tsb35 tsb34 tsb33 tsb32 tsb31 tsb30 a3) 70 tss2 tss24 tss23 tss22 tss21 tss20 (a4) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 422 ds1.1, 2003-10-23 hardware description time slot select 3 (read/write) value after reset: 00 h tss3(4:0) time slot selection code - hdlc channel 3 defines the time slot used by hdlc channel 3. 00000 =no time slot selected 00001 =time slot 1 ... 11111 =time slot 31 note: different hdlc channels must use different time slots. test pattern control register 0 (read/write) value after reset: 00 h fra framed/unframed selection 0 = prbs is generated/monitored unframed. framing information is overwritten by the generator. 1 = prbs is generated/monitored framed. time slot 0 is not overwritten by the generator and not observed by the monitor. 70 tss3 tss34 tss33 tss32 tss31 tss30 (a5) 70 tpc0 fra (a8) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 423 ds1.1, 2003-10-23 hardware description global line control register 1 (read/write) value after reset: 00 h rlrrw receive line ram read/write select 0 = read access 1 = write access ers receive line ram access enable 0 = ram access disabled 1 = ram access enabled attention: as long as ers = 1 is selected, only ram access is possible and no register can be read or written to. a read acces to address f8h clears ers and enables normal operation. 70 glc1 0 0 0 0 0 0 ramrw ramen (af) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 424 ds1.1, 2003-10-23 hardware description 10.3 t1/j1 status register addresses table 72 t1/j1 status register address arrangement address register type comment page 00 rfifo r receive fifo 426 01 rfifo r receive fifo 426 49 rbd r receive buffer delay 426 4a vstr r version status register 427 4b res r receive equalizer status 427 4c frs0 r framer receive status 0 428 4d frs1 r framer receive status 1 430 4e frs2 r framer receive status 2 432 50 fecl r framing error counter low 433 51 fech r framing error counter high 433 52 cvcl r code violation counter low 434 53 cvch r code violation counter high 434 54 cecl r crc error counter low 435 55 cech r crc error counter high 435 56 ebcl r errored block counter low 436 57 ebch r errored block counter high 436 58 becl r bit error counter low 437 59 bech r bit error counter high 437 5a coec r cofa event counter 438 5c rdl1 r receive dl-bit register 1 439 5d rdl2 r receive dl-bit register 2 439 5e rdl3 r receive dl-bit register 3 440 62 rsp1 r receive signaling pointer 1 440 63 rsp2 r receive signaling pointer 2 440 64 sis r signaling status register 441 65 rsis r receive signaling status register 442 66 rbcl r receive byte control low 444 67 rbch r receive byte control high 444 68 isr0 r interrupt status register 0 445 falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 425 ds1.1, 2003-10-23 hardware description 69 isr1 r interrupt status register 1 447 6a isr2 r interrupt status register 2 448 6b isr3 r interrupt status register 3 450 6c isr4 r interrupt status register 4 451 6d isr5 r interrupt status register 5 453 6e gis r global interrupt status 455 70 rs1 r receive signaling register 1 456 71 rs2 r receive signaling register 2 456 72 rs3 r receive signaling register 3 456 73 rs4 r receive signaling register 4 456 74 rs5 r receive signaling register 5 456 75 rs6 r receive signaling register 6 456 76 rs7 r receive signaling register 7 456 77 rs8 r receive signaling register 8 456 78 rs9 r receive signaling register 9 456 79 rs10 r receive signaling register 10 456 7a rs11 r receive signaling register 11 456 7b rs12 r receive signaling register 12 456 90 rbc2 r receive byte count register 2 457 91 rbc3 r receive byte count register 3 457 a9 sis2 r signaling status register 2 457 aa rsis2 r receive signaling status register 2 458 9a sis3 r signaling status register 3 460 9b rsis3 r receive signaling status register 3 461 9c rfifo2 r receive fifo 2 463 9d rfifo2 r receive fifo 2 463 9e rfifo3 r receive fifo 3 463 9f rfifo3 r receive fifo 3 463 ab mfpi r multi function port input status 463 table 72 t1/j1 status register address arrangement (cont?d) address register type comment page falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 426 ds1.1, 2003-10-23 hardware description 10.4 detailed description of t1/j1 status registers receive fifo - hdlc channel 1 (read) reading data from rfifo can be done in an 8-bit (byte) or 16-bit (word) access depending on the selected bus interface mode. the lsb is received first from the serial interface. the size of the accessible part of rfifo is determined by programming the bits ccr1.rft(1 : 0) (rfifo threshold level). it can be reduced from 32 bytes (reset value) down to 2 bytes (four values: 32, 16, 4, 2 bytes). data transfer up to 32 bytes/16 words of received data can be read from the rfifo following a rpf or a rme interrupt. rpf interrupt: a fixed number of bytes/words to be read (32, 16, 4, 2 bytes). the message is not yet complete. rme interrupt: the message is completely received. the number of valid bytes is determined by reading the rbcl, rbch registers. rfifo is released by issuing the rmc ( r eceive m essage c omplete) command. receive buffer delay (read) rbd(5:0) receive elastic buffer delay these bits informs the user about the current delay (in time slots) through the receive elastic buffer. the delay is updated every 386 or 193 bits (sic1.rbs(1:0)). before reading this register the user has to set bit dec.drbd in order to halt the current value of this register. after reading rbd updating of this register is enabled. not valid if the receive buffer is bypassed. 000000 = delay < 1 time slot ... 111111 = delay > 63 time slots 70 rfifo rf7 rf0 (00) rfifo rf15 rf8 (01) 70 rbd rbd5 rbd4 rbd3 rbd2 rbd1 rbd0 (49) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 427 ds1.1, 2003-10-23 hardware description version status register (read) vn(7:0) version number of chip 00 h =version 1.2 10 h =version 2.1 receive equalizer status (read) ev(1:0) equalizer status valid these bits informs the user about the current state of the receive equalization network. 00 = equalizer status not valid, still adapting 01 = equalizer status valid 10 = equalizer status not valid 11 = equalizer status valid but high noise floor res(4:0) receive equalizer status the current line attenuation status in steps of about 1.4 db are displayed in these bits. only valid if bits ev(1:0) = 01. accuracy: 2 digits, based on temperature influence and noise amplitude variations. 00000 = minimum attenuation: 0 db ... 11001 = maximum attenuation: -36 db 70 vstr vn7 vn0 (4a) 70 res ev1 ev0 res4 res3 res2 res1 res0 (4b) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 428 ds1.1, 2003-10-23 hardware description framer receive status register 0 (read) los loss-of-signal (red alarm) detection: this bit is set when the incoming signal has ?no transitions? (analog interface) or logical zeros (digital interface) in a time interval of t consecutive pulses, where t is programmable by pcd register: total account of consecutive pulses: 16 < t < 4096. analog interface: the receive signal level where ?no transition? is declared is defined by the programmed value of lim1.ril(2:0). recovery: analog interface: the bit is reset in short-haul mode when the incoming signal has transitions with signal levels greater than the programmed receive input level (lim1.ril(2:0)) for at least m pulse periods defined by register pcr in the pcd time interval. in long-haul mode additionally bit res.6 must be set for at least 250 s. digital interface: the bit is reset when the incoming data stream contains at least m ones defined by register pcr in the pcd time interval. with the rising edge of this bit an interrupt status bit (isr2.los) is set. for additionally recovery conditions refer also to register lim2.los1. the bit is set during alarm simulation and reset if frs2.esc = 0, 3, 4, 6,7 and no alarm condition exists. ais alarm indication signal (blue alarm) this bit is set when the conditions defined by bit fmr4.ais3 are detected. the flag stays active for at least one multiframe. with the rising edge of this bit an interrupt status bit (isr2.ais) is set. it is reset with the beginning of the next following multiframe if no alarm condition is detected. the bit is set during alarm simulation and reset if frs2.esc = 0, 3, 4, 7 and no alarm condition exists. 70 frs0 los ais lfa rra lmfa fsrf (4c) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 429 ds1.1, 2003-10-23 hardware description lfa loss of frame alignment the flag is set if pulseframe synchronization has been lost. the conditions are specified by bit fmr4.ssc(1:0). setting this bit causes an interrupt (isr2.lfa). the flag is cleared when synchronization has been regained. additionally interrupt status isr2.far is set with clearing this bit. rra receive remote alarm (yellow alarm) the flag is set after detecting remote alarm (yellow alarm). conditions for setting/resetting are defined by bit rc0.rram. with the rising edge of this bit an interrupt status bit isr2.ra is set. with the falling edge of this bit an interrupt status bit isr2.rar is set. the bit is set during alarm simulation and reset if frs2.esc = 0, 3, 4,5,7 and no alarm condition exists. lmfa loss of multiframe alignment set in f12 or f72 format when 2 out of 4 (or 5 or 6) multiframe alignment patterns are incorrect. additionally the interrupt status bit isr2.lmfa is set. cleared after multiframe synchronization has been regained. with the falling edge of this bit an interrupt status bit isr2.mfar is generated. fsrf frame search restart flag toggles when no framing candidate (pulse framing or multiframing) is found and a new frame search is started. falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 430 ds1.1, 2003-10-23 hardware description framer receive status register 1 (read) exzd excessive zeros detected significant only if excessive zeros detection is enabled (fmr2.exze = 1). set after detecting of more than 7 (b8zs code) or more than 15 (ami code) contiguous zeros in the received bit stream. this bit is cleared on read. pden pulse-density violation detected the pulse-density of the received data stream is below the requirement defined by ansi t1. 403 or more than 14 consecutive zeros are detected. with the violation of the pulse-density this bit is set and remains active until the pulse-density requirement is fulfilled for 23 consecutive "1"-pulses. additionally an interrupt status isr0.pden is generated with the rising edge of pden. llbdd line loop-back deactivation signal detected this bit is set in case of the llb deactivate signal is detected and then received over a period of more than 33.16 ms with a bit error rate less than 10 -2 . the bit remains set as long as the bit error rate does not exceed 10 -2 . if framing is aligned, the first bit position of any frame is not taken into account for the error rate calculation. any change of this bit causes an llbsc interrupt. llbad line loop-back activation signal detected/prbs status depending on bit lcr1.eprm the source of this status bit changed. lcr1.eprm = 0: this bit is set in case of the llb activate signal is detected and then received over a period of more than 33.16 ms with a bit error rate less than 10 -2 . the bit remains set as long as the bit error rate does not exceed 10 -2 . if framing is aligned, the first bit position of any frame is not taken into account for the error rate calculation. any change of this bit causes an llbsc interrupt. 70 frs1 exzd pden llbdd llbad xls xlo (4d) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 431 ds1.1, 2003-10-23 hardware description prbs status lcr1.eprm = 1: the current status of the prbs synchronizer is indicated in this bit. it is set high if the synchronous state is reached even in the presence of a bit error rate of up to 10 -3 . a data stream containing all zeros or all ones with/without framing bits is also a valid pseudo-random binary sequence. xls transmit line short significant only if the ternary line interface is selected by lim1.drs = 0. 0 = normal operation. no short is detected. 1 = the xl1 and xl2 are shortened for at least 3 pulses. as a reaction of the short the pins xl1 and xl2 are automatically forced into a high-impedance state if bit xpm2.daxlt is reset. after 128 consecutive pulse periods the outputs xl1/2 are activated again and the internal transmit current limiter is checked. if a short between xl1/2 is still further active the outputs xl1/2 are in high-impedance state again. when the short disappears pins xl1/2 are activated automatically and this bit is reset. with any change of this bit an interrupt isr1.xlsc is generated. in case of xpm2.xlt is set this bit is frozen. xlo transmit line open 0 = normal operation 1 = this bit is set if at least 32 consecutive zeros were sent on pins xl1/xl2 or xdop/xdon. this bit is reset with the first transmitted pulse. with the rising edge of this bit an interrupt isr1.xlsc is set. in case of xpm2.xlt is set this bit is frozen. falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 432 ds1.1, 2003-10-23 hardware description framer receive status register 2 (read) esc(2:0) error simulation counter this three-bit counter is incremented by setting bit fmr0.sim. the state of the counter determines the function to be tested. for complete checking of the alarm indications, eight simulation steps are necessary (frs2.esc = 0 after a complete simulation). 70 frs2 esc2 esc1 esc0 (4e) table 73 alarm simulation states tested alarms esc(2:0)= 01234567 lfa lmfa rra (bit2 = 0) rra (s-bit frame 12) rra (dl-pattern) los 1) 1) only active during fmr0.sim = 1 ebc 2) (f12,f72) 2) fec is counting +2 while ebc is counting +1 if the framer is in synchronous state; if asynchronous in state 2 but synchronous in state 6, counters are incremented during state 6 () ebc 2) (only esf) () ais 1) fec 2) () cvc cec (only esf) rsp rsn xsp xsn bec 1) coec falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 433 ds1.1, 2003-10-23 hardware description some of these alarm indications are simulated only if the falc ? 56 is configured in the appropriate mode. at simulation steps 0, 3, 4, and 7 pending status flags are reset automatically and clearing of the error counters and interrupt status registers isr(5:0) should be done. incrementing the simulation counter should not be done at time intervals shorter than 1.5 ms (f4, f12, f72) or 3 ms (esf). otherwise, reactions of initiated simulations might occur at later steps. control bit fmr0.sim has to be held stable at high or low level for at least one receive clock period before changing it again. framing error counter (read) fe(15:0) framing errors this 16-bit counter is incremented when incorrect ft and fs-bits in f4, f12 and f72 format or incorrect fas-bits in esf format are received. framing errors are counted during synchronous state only (but even if multiframe synchronous state is not reached yet). the error counter does not roll over. during alarm simulation, the counter is incremented twice. clearing and updating the counter is done according to bit fmr1.ecm. if this bit is reset the error counter is permanently updated in the buffer. for correct read access of the error counter bit dec.dfec has to be set. with the rising edge of this bit updating the buffer is stopped and the error counter is reset. bit dec.dfec is automatically reset with reading the error counter high byte. if fmr1.ecm is set every second (interrupt isr3.sec) the error counter is latched and then automatically reset. the latched error counter state should be read within the next second. 70 fecl fe7 fe0 (50) 70 fech fe15 fe8 (51) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 434 ds1.1, 2003-10-23 hardware description code violation counter (read) cv(15:0) code violations no function if nrz or cmi code has been enabled. if the b8zs code (bit fmr0.rc(1:0) = 11) is selected, the 16-bit counter is incremented by detecting violations which are not due to zero substitution. if fmr2.exze is set, additionally excessive zero strings (more than 7 contiguous zeros) are detected and counted. if simple ami coding is enabled (fmr0.rc0/1 = 10) all bipolar violations are counted. if fmr2.exze is set, additionally excessive zero strings (more than 15 contiguous zeros) are detected and counted. the error counter does not roll over. during alarm simulation, the counter is incremented continuously with every second received bit. clearing and updating the counter is done according to bit fmr1.ecm. if this bit is reset the error counter is permanently updated in the buffer. for correct read access of the error counter bit dec.dcvc has to be set. with the rising edge of this bit updating the buffer is stopped and the error counter is reset. bit dec.dcvc is automatically reset with reading the error counter high byte. if fmr1.ecm is set every second (interrupt isr3.sec) the error counter is latched and then automatically reset. the latched error counter state should be read within the next second. 70 cvcl cv7 cv0 (52) 70 cvch cv15 cv8 (53) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 435 ds1.1, 2003-10-23 hardware description crc error counter (read) cr(15:0) crc errors no function if crc6 procedure or esf format are disabled. in esf mode, the 16-bit counter is incremented when a multiframe has been received with a crc error. crc errors are not counted during asynchronous state. the error counter does not roll over. during alarm simulation, the counter is incremented once per multiframe. clearing and updating the counter is done according to bit fmr1.ecm. if this bit is reset the error counter is permanently updated in the buffer. for correct read access of the error counter bit dec.dcec has to be set. with the rising edge of this bit updating the buffer is stopped and the error counter is reset. bit dec.dcec is automatically reset with reading the error counter high byte. if fmr1.ecm is set every second (interrupt isr3.sec) the error counter is latched and then automatically reset. the latched error counter state should be read within the next second. 70 cecl cr7 cr0 (54) 70 cech cr15 cr8 (55) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 436 ds1.1, 2003-10-23 hardware description errored block counter (read) ebc(15:0) errored block counter in esf format this 16-bit counter is incremented once per multiframe if a multiframe has been received with a crc error or an errored frame alignment has been detected. crc and framing errors are not counted during asynchronous state. the error counter does not roll over. in f4/12/72 format an errored block contain 4/12 or 72 frames. incrementing is done once per multiframe if framing errors has been detected. during alarm simulation, the counter is incremented in esf format once per multiframe and in f4/12/72 format only one time. clearing and updating the counter is done according to bit fmr1.ecm. if this bit is reset the error counter is permanently updated in the buffer. for correct read access of the error counter bit dec.debc has to be set. with the rising edge of this bit updating the buffer is stopped and the error counter is reset. bit dec.debc is automatically reset with reading the error counter high byte. if fmr1.ecm is set every second (interrupt isr3.sec) the error counter is latched and then automatically reset. the latched error counter state should be read within the next second. 70 ebcl ebc7 ebc0 (56) 70 ebch ebc15 ebc8 (57) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 437 ds1.1, 2003-10-23 hardware description bit error counter (read) bec(15:0) bit error counter if the prbs monitor is enabled by lcr1.eprm = 1 this 16-bit counter is incremented with every rece ived prbs bit error in the prbs synchronous state frs1.llbad = 1. the error counter does not roll over. during alarm simulation, the counter is incremented continuously with every second received bit. clearing and updating the counter is done according to bit fmr1.ecm. if this bit is reset the error counter is permanently updated in the buffer. for correct read access of the prbs bit error counter bit dec.dbec has to be set. with the rising edge of this bit updating the buffer is stopped and the error counter is reset. bit dec.dbec is automatically reset with reading the error counter high byte. if fmr1.ecm is set every second (interrupt isr3.sec) the error counter is latched and then automatically reset. the latched error counter state should be read within the next second. 70 becl bec7 bec0 (58) 70 bech bec15 bec8 (59) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 438 ds1.1, 2003-10-23 hardware description cofa event counter (read) coe(7:2) multiframe counter if gcr.ecmc = 1 this 6 bit counter increments with each multiframe period in the asynchronous state frs0.lfa/lmfa = 1. the error counter does not roll over. coe(1:0) change of frame alignment counter if gcr.ecmc = 1 this 2 bit counter increments with each detected change of frame/multiframe alignment. the error counter does not roll over. during alarm simulation, the counter is incremented once per multiframe. clearing and updating the counter is done according to bit fmr1.ecm. if this bit is reset the error counter is permanently updated in the buffer. for correct read access of the event counter bit dec.dcoec has to be set. with the rising edge of this bit updating the buffer is stopped and the error counter is reset. bit dec.dcoec is automatically reset with reading the error counter high byte on address 5b h . data read on 5b h is not defined. if fmr1.ecm is set every second (interrupt isr3.sec) the error counter is latched and then automatically reset. the latched error counter state should be read within the next second. 70 coec coe7 coe2 coe1 coe0 (5a) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 439 ds1.1, 2003-10-23 hardware description receive dl-bit register 1 (read) rdl1(7:0) receive dl-bit only valid if f12, f24 or f72 format is enabled. the received fs/dl-bits are shifted into this register. rdl10 is received in frame 1 and rdl17 in frame 15, if f24 format is enabled. rdl10 is received in frame 26 and rdl17 in frame 40, if f72 format is enabled. in f12 format the fs-bits of a complete multiframe is stored in this register. rdl10 is received in frame 2 and rdl15 in frame 12. this register is updated with every receive multiframe begin interrupt isr0.rmb. receive dl-bit register 2 (read) rdl2(7:0) receive dl-bit only valid if f24 or f72 format is enabled. the received dl-bits are shifted into this register. rdl20 is received in frame 17 and rdl23 in frame 23, if f24 format is enabled. rdl20 is received in frame 42 and rdl27 in frame 56, if f72 format is enabled. this register is updated with every receive multiframe begin interrupt isr0.rmb. 70 rdl1 rdl17 rdl16 rdl15 rdl14 rdl13 rdl12 rdl11 rdl10 (5c) 70 rdl2 rdl27 rdl26 rdl25 rdl24 rdl23 rdl22 rdl21 rdl20 (5d) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 440 ds1.1, 2003-10-23 hardware description receive dl-bit register 3 (read) rdl3(7:0) receive dl-bit only valid if f72 format is enabled. the received dl-bits are shifted into this register. rdl30 is received in frame 58 and rdl37 in frame 72, if f72 format is enabled. this register is updated with every receive multiframe begin interrupt isr0.rmb. receive signaling pointer 1 (read) value after reset: 00 h rs(8:1)c receive signaling register rs(8:1) changed a one in each bit position indicates that the received signaling data in the corresponding rs(8:1) registers are updated. bit rs1c is the pointer for register rs1, while rs8c points to rs8. receive signaling pointer 2 (read) value after reset: 00 h rs(12:0)c receive signaling register rs(12:9) changed a one in each bit position indicates that the received signaling data in the corresponding rs(12:9) registers are updated. bit rs9c is the pointer for register rs9, while rs12c points to rs12 70 rdl3 rdl37 rdl36 rdl35 rdl34 rdl33 rdl32 rdl31 rdl30 (5e) 70 rsp1 rs8c rs7c rs6c rs5c rs4c rs3c rs2c rs1c (62) 70 rsp2 rs12c rs11c rs10c rs9c (63) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 441 ds1.1, 2003-10-23 hardware description signaling status register (read) xdov transmit data overflow - hdlc channel 1 more than 32 bytes have been written to the xfifo. this bit is reset ? by a transmitter reset command xres or ? when all bytes in the accessible half of the xfifo have been moved in the inaccessible half. xfw transmit fifo write enable - hdlc channel 1 data can be written to the xfifo. xrep transmission repeat - hdlc channel 1 status indication of cmdr.xrep. ivb invalid bom frame received - hdlc channel 1 0 = valid bom frame (11111111, 0xxxxxx0) received. 1 = invalid bom frame received. rli receive line inactive - hdlc channel 1 neither flags as interframe time fill nor frames are received in the signaling time slot. cec command executing 0 = no command is currently executed, the cmdr register can be written to. 1 = a command (written previously to cmdr) is currently executed, no further command can be temporarily written in cmdr register. note: cec is active at most 2.5 periods of the current system data rate. sfs status freeze signaling 0 = freeze signaling status inactive. 1 = freeze signaling status active. 70 sis xdov xfw xrep ivb rli cec sfs bom (64) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 442 ds1.1, 2003-10-23 hardware description bom bit oriented message - hdlc channel 1 significant only in esf frame format and auto switching mode is enabled. 0 = hdlc mode 1 = bom mode receive signaling status register (read) rsis relates to the last received hdlc or bom frame; it is copied into rfifo when end-of-frame is recognized (last byte of each stored frame). vfr valid frame - hdlc channel 1 determines whether a valid frame has been received. 1 = valid 0 = invalid an invalid frame is either ? a frame which is not an integer number of 8 bits (n 8 bits) in length (e.g. 25 bits), or ? a frame which is too short taking into account the operation mode selected by mode (mds(2:0)) and the selection of receive crc on/off (ccr2.rcrc) as follows: mds(2:0) = 011 (16 bit address), rcrc = 0: 4 bytes; rcrc = 1: 3 or 4 bytes mds(2:0) = 010 (8 bit address), rcrc = 0: 3 bytes; rcrc = 1: 2 or 3 bytes note:shorter frames are not reported. rdo receive data overflow - hdlc channel 1 a data overflow has occurred during reception of the frame. additionally, an interrupt can be generated (refer to isr1.rdo/imr1.rdo). crc16 crc16 compare/check - hdlc channel 1 0 = crc check failed; received frame contains errors. 1 = crc check o.k.; received frame is error-free. 70 rsis vfr rdo crc16 rab ha1 ha0 hfr la (65) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 443 ds1.1, 2003-10-23 hardware description rab receive message aborted - hdlc channel 1 this bit is set in ss7 mode, if the maximum number of octets (272+7) is exceeded. the received frame was aborted from the transmitting station. according to the hdlc protocol, this frame must be discarded by the receiver station. ha1, ha0 high byte address compare - hdlc channel 1 significant only if 2-byte address mode or ss7 mode has been selected. in operating modes which provide high byte address recognition, the falc ? 56 compares the high byte of a 2-byte address with the contents of two individually programmable registers (rah1, rah2) and the fixed values fe h and fc h (broadcast address). depending on the result of this comparison, the following bit combinations are possible (ss7 support not active): 00 = rah2 has been recognized 01 = broadcast address has been recognized 10 = rah1 has been recognized c/r = 0 (bit 1) 11 = rah1 has been recognized c/r = 1 (bit 1) note: if rah1, rah2 contain identical values, a match is indicated by "10" or "11". if signaling system 7 support is activated (see mode register), the bit functions are defined as follows: 00 = not valid 01 = fill in signaling unit (fisu) detected 10 = link status signaling unit (lssu) detected 11 = message signaling unit (msu) detected hfr hdlc frame format - hdlc channel 1 0 = a bom frame was received. 1 = a hdlc frame was received. note: bits rsis.(7:2) and rsis.0 are not valid with a bom frame. this means, if hfr = 0, all other bits of rsis have to be ignored not valid in ss7 mode. bit hfr has to be ignored, if ss7 mode is selected. falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 444 ds1.1, 2003-10-23 hardware description la low byte address compare - hdlc channel 1 significant in hdlc modes only. the low byte address of a 2-byte address field, or the single address byte of a 1-byte address field is compared to two registers. (ral1, ral2). 0 = ral2 has been recognized 1 = ral1 has been recognized note:not valid in ss7 mode. bit la has to be ignored, if ss7 mode is selected. receive byte count low - hdlc channel 1 (read) together with rbch, bits rbc(11:8), indicates the length of a received frame (1 to 4095 bytes). bits rbc(4:0) indicate the number of valid bytes currently in rfifo. these registers must be read by the cpu following a rme interrupt. received byte count high - hdlc channel 1 (read) ov counter overflow - hdlc channel 1 more than 4095 bytes received. rbc(11:8) receive byte count - hdlc channel 1 (most significant bits) together with rbcl (bits rbc(7 : 0)) indicates the length of the received frame. 70 rbcl rbc7 rbc0 (66) 70 rbch ov rbc11 rbc10 rbc9 rbc8 (67) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 445 ds1.1, 2003-10-23 hardware description interrupt status register 0 (read) value after reset: 00 h all bits are reset when isr0 is read. if bit gcr.vis is set, interrupt statuses in isr0 are flagged although they are masked by register imr0. however, these masked interrupt statuses neither generate a signal on int, nor are visible in register gis. rme receive message end - hdlc channel 1 one complete message of length less than 32 bytes, or the last part of a frame at least 32 bytes long is stored in the receive fifo, including the status byte. the complete message length can be determined reading the rbch, rbcl registers, the number of bytes currently stored in rfifo is given by rbc(4:0). additional information is available in the rsis register. rfs/biv receive frame start - hdlc channel 1 this is an early receiver interrupt activated after the start of a valid frame has been detected, i.e. after an address match (in operation modes providing address recognition), or after the opening flag (transparent mode 0) is detected, delayed by two bytes. after a rfs interrupt, the contents of ral1and rsis.3-1 are valid and can be read by the cpu. bom frame invalid - hdlc channel 1 only valid if ccr2.rbfe is set. when the bom receiver left the valid bom status (detecting 7 out of 10 equal bom frames) this interrupt is generated. isf incorrect sync format - hdlc channel 1 the falc ? 56 did not detect eight consecutive ones within 32 bits in bom mode. only valid if bom receiver has been activated. rmb receive multiframe begin this bit is set with the beginning of a received multiframe of the receive line timing. 70 isr0 rme rfs/biv isf rmb rsc crc6 pden rpf (68) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 446 ds1.1, 2003-10-23 hardware description rsc received signaling information changed this interrupt bit is set during each multiframe in which signaling information on at least one channel changes its value from the previous multiframe. this interrupt only occurs in the synchronous state. the registers rs(12:1) should be read within the next 3 ms otherwise the contents is lost. crc6 receive crc6 error 0 = no crc6 error occurs. 1 = the crc6 check of the last received multiframe failed. pden pulse-density violation the pulse-density violation of the received data stream defined by ansi t1. 403 is violated. more than 14 consecutive zeros or less than n ones in each and every time window of 8 (n+1) data bits (n = 23) are detected. if gcr.sci is set high this interrupt status bit is activated with every change of state of frs1.pden. rpf receive pool full - hdlc channel 1 32 bytes of a frame have arrived in the receive fifo. the frame is not yet received completely. falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 447 ds1.1, 2003-10-23 hardware description interrupt status register 1 (read) all bits are reset when isr1 is read. if bit gcr.vis is set, interrupt statuses in isr1 are flagged although they are masked by register imr1. however, these masked interrupt statuses neither generate a signal on int, nor are visible in register gis. case transmit cas register empty in esf format this bit is set with the beginning of a transmitted multiframe related to the internal transmitter timing. in f12 and f72 format this interrupt occurs every 24 frames to inform the user that new bit robbing data may be written to the xs(12:1) registers. this interrupt is generated only if the serial signaling access on the system highway is not enabled. rdo receive data overflow - hdlc channel 1 this interrupt status indicates that the cpu did not respond fast enough to an rpf or rme interrupt and that data in rfifo has been lost. even when this interrupt status is generated, the frame continues to be received when space in the rfifo is available again. note: whereas the bit rsis.rdo in the frame status byte indicates whether an overflow occurred when receiving the frame currently accessed in the rfifo, the isr1.rdo interrupt status is generated as soon as an overflow occurs and does not necessarily pertain to the frame currently accessed by the processor. alls all sent - hdlc channel 1 this bit is set if the last bit of the current frame has been sent completely and xfifo is empty. this bit is valid in hdlc mode only. xdu transmit data underrun - hdlc channel 1 transmitted frame was terminated with an abort sequence because no data was available for transmission in xfifo and no xme was issued. note: transmitter and xfifo are reset and deactivated if this condition occurs. they are reactivated not before this interrupt status register has been read. thus, xdu should not be masked by register imr1. 70 isr1 case rdo alls xdu xmb suex xlsc xpr (69) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 448 ds1.1, 2003-10-23 hardware description xmb transmit multiframe begin this bit is set with the beginning of a transmitted multiframe related to the internal transmit line interface timing. suex signaling unit error threshold exceeded - hdlc channel 1 masks the indication by interrupt that the selected error threshold for ss7 signaling units has been exceeded. 0 = signaling unit error count below selected threshold 1 = signaling unit error count exceeded selected threshold note:suex is only valid, if ss7 mode is selected. if suex is caused by an aborted/invalid frame, the interrupt will be issued regularly until a valid frame is received (e.g. a fisu). xlsc transmit line status change xlsc is set with the rising edge of the bit frs1.xlo or with any change of bit frs1.xls. the actual status of the transmit line monitor can be read from the frs1.xls and frs1.xlo. xpr transmit pool ready - hdlc channel 1 a data block of up to 32 bytes can be written to the transmit fifo. xpr enables the fastest access to xfifo. it has to be used for transmission of long frames, back-to-back frames or frames with shared flags. interrupt status register 2 (read) all bits are reset when isr2 is read. if bit gcr.vis is set, interrupt statuses in isr2 are flagged although they are masked by register imr2. however, these masked interrupt statuses neither generate a signal on int, nor are visible in register gis. far frame alignment recovery the framer has reached synchronization. set with the falling edge of bit frs0.lfa. it is set also after alarm simulation is finished and the receiver is still synchronous. 70 isr2 far lfa mfar lmfa ais los rar ra (6a) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 449 ds1.1, 2003-10-23 hardware description lfa loss of frame alignment the framer has lost synchronization and bit frs0.lfa is set. it is set during alarm simulation. mfar multiframe alignment recovery set when the framer has reached multiframe alignment in f12 or f72 format. with the negative transition of bit frs0.lmfa this bit is set. it is set during alarm simulation. lmfa loss of multiframe alignment set when the framer has lost the multiframe alignment in f12 or f72 format. with the positive transition of bit frs0.lmfa this bit is set. it is set during alarm simulation. ais alarm indication signal (blue alarm) this bit is set when an alarm indication signal is detected and bit frs0.ais is set. if gcr.sci is set high this interrupt status bit is activated with every change of state of frs0.ais. it is set during alarm simulation. los loss-of-signal (red alarm) this bit is set when a loss-of-signal alarm is detected in the received data stream and frs0.los is set. if gcr.sci is set high this interrupt status bit is activated with every change of state of frs0.los. it is set during alarm simulation. rar remote alarm recovery set if a remote alarm (yellow alarm) is cleared and bit frs0.rra is reset. it is set also after alarm simulation is finished and no remote alarm is detected. ra remote alarm a remote alarm (yellow alarm) is detected. set with the rising edge of bit frs0.rra. it is set during alarm simulation. falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 450 ds1.1, 2003-10-23 hardware description interrupt status register 3 (read) all bits are reset when isr3 is read. if bit gcr.vis is set, interrupt statuses in isr3 are flagged although they are masked by register imr3. however, these masked interrupt statuses neither generate a signal on int, nor are visible in register gis. es errored second this bit is set if at least one enabled interrupt source by esm is set during the time interval of one second. interrupt sources of esm register: lfa = loss of frame alignment detected fer = framing error received cer = crc error received ais = alarm indication signal (blue alarm) los = loss-of-signal (red alarm) cve = code violation detected slip = transmit slip or receive slip positive/negative detected sec second timer the internal one-second timer has expired. the timer is derived from clock rclk. llbsc line loop-back status change/prbs status change depending on bit lcr1.eprm the source of this interrupt status changed: lcr1.eprm = 0: this bit is set, if the llb activate signal or the llb deactivate signal is detected over a period of 33.16 ms with a bit error rate less than 10 -2 . the llbsc bit is also set, if the current detection status is left, i.e., if the bit error rate exceeds 10 -2 . the actual detection status can be read from the frs1.llbad and frs1.llbdd, respectively. prbs status change lcr1.eprm = 1: with any change of state of the prbs synchronizer this bit is set. the current status of the prbs synchronizer is indicated in frs1.llbad. 70 isr3 es sec llbsc rsn rsp (6b) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 451 ds1.1, 2003-10-23 hardware description rsn receive slip negative the frequency of the receive route clock is greater than the frequency of the receive system interface working clock based on 1.544 mhz. a frame is skipped. it is set during alarm simulation. rsp receive slip positive the frequency of the receive route clock is less than the frequency of the receive system interface working clock based on 1.544 mhz. a frame is repeated. it is set during alarm simulation. interrupt status register 4 (read) all bits are reset when isr4 is read. if bit gcr.vis is set, interrupt statuses in isr4 are flagged although they are masked by register imr4. however, these masked interrupt statuses neither generate a signal on int, nor are visible in register gis. xsp transmit slip positive the frequency of the transmit clock is less than the frequency of the transmit system interface working clock based on 1.544 mhz. a frame is repeated. after a slip has performed writing of register xc1 is not necessary. xsn transmit slip negative the frequency of the transmit clock is greater than the frequency of the transmit system interface working clock based on 1.544 mhz. a frame is skipped. after a slip has performed writing of register xc1 is not necessary. rme2 receive message end - hdlc channel 2 one complete message of length less than 32 bytes, or the last part of a frame at least 32 bytes long is stored in the receive fifo2, including the status byte. the complete message length can be determined reading register rbc2, the number of bytes currently stored in rfifo2 is given by rbc2(6:0). additional information is available in register rsis2. 70 isr4 xsp xsn rme2 rfs2 rdo2 alls2 xdu2 rpf2 (6c) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 452 ds1.1, 2003-10-23 hardware description rfs2 receive frame start - hdlc channel 2 this is an early receiver interrupt activated after the start of a valid frame has been detected, i.e. after an address match (in operation modes providing address recognition), or after the opening flag (transparent mode 0) is detected, delayed by two bytes. after an rfs2 interrupt, the contents of ral1 rsis2 bits 3 to 1 are valid and can be read by the cpu. rdo2 receive data overflow - hdlc channel 2 this interrupt status indicates that the cpu did not respond fast enough to an rpf2 or rme2 interrupt and that data in rfifo2 has been lost. even when this interrupt status is generated, the frame continues to be received when space in the rfifo2 is available again. note: whereas the bit rsis2.rdo2 in the frame status byte indicates whether an overflow occurred when receiving the frame currently accessed in the rfifo2, the isr4.rdo2 interrupt status is generated as soon as an overflow occurs and does not necessarily pertain to the frame currently accessed by the processor. alls2 all sent - hdlc channel 2 this bit is set if the last bit of the current frame has been sent completely and xfifo2 is empty. this bit is valid in hdlc mode only. xdu2 transmit data underrun - hdlc channel 2 transmitted frame was terminated with an abort sequence because no data was available for transmission in xfifo2 and no xme2 was issued. note: transmitter and xfifo2 are reset and deactivated if this condition occurs. they are reactivated not before this interrupt status register has been read. thus, xdu2 should not be masked via register imr4. rpf2 receive pool full - hdlc channel 2 32 bytes of a frame have arrived in the receive fifo2. the frame is not yet completely received. falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 453 ds1.1, 2003-10-23 hardware description interrupt status register 5 (read) all bits are reset when isr5 is read. if bit gcr.vis is set, interrupt statuses in isr5 are flagged although they are masked via register imr5. however, these masked interrupt statuses neither generate a signal on int, nor are visible in register gis. xpr2 transmit pool ready - hdlc channel 2 a data block of up to 32 bytes can be written to the transmit fifo2. xpr2 enables the fastest access to xfifo2. it has to be used for transmission of long frames, back-to-back frames or frames with shared flags. xpr3 transmit pool ready - hdlc channel 3 a data block of up to 32 bytes can be written to the transmit fifo3. xpr3 enables the fastest access to xfifo3. it has to be used for transmission of long frames, back-to-back frames or frames with shared flags. rme3 receive message end - hdlc channel 3 one complete message of length less than 32 bytes, or the last part of a frame at least 32 bytes long is stored in the receive fifo3, including the status byte. the complete message length can be determined reading register rbc3, the number of bytes currently stored in rfifo3 is given by rbc3(6:0). additional information is available in register rsis3. rfs3 receive frame start - hdlc channel 3 this is an early receiver interrupt activated after the start of a valid frame has been detected, i.e. after an address match (in operation modes providing address recognition), or after the opening flag (transparent mode 0) is detected, delayed by two bytes. after an rfs2 interrupt, the contents of ral1 rsis3 bits 3 to 1 are valid and can be read by the cpu. 70 isr5 xpr2 xpr3 rme3 rfs3 rdo3 alls3 xdu3 rpf3 (6d) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 454 ds1.1, 2003-10-23 hardware description rdo3 receive data overflow - hdlc channel 3 this interrupt status indicates that the cpu did not respond fast enough to an rpf3 or rme3 interrupt and that data in rfifo3 has been lost. even when this interrupt status is generated, the frame continues to be received when space in the rfifo3 is available again. note: whereas the bit rsis3.rdo3 in the frame status byte indicates whether an overflow occurred when receiving the frame currently accessed in the rfifo3, the isr5.rdo3 interrupt status is generated as soon as an overflow occurs and does not necessarily pertain to the frame currently accessed by the processor. alls3 all sent - hdlc channel 3 this bit is set if the last bit of the current frame has been sent completely and xfifo3 is empty. this bit is valid in hdlc mode only. xdu3 transmit data underrun - hdlc channel 3 transmitted frame was terminated with an abort sequence because no data was available for transmission in xfifo3 and no xme3 was issued. note: transmitter and xfifo3 are reset and deactivated if this condition occurs. they are reactivated not before this interrupt status register has been read. thus, xdu3 should not be masked via register imr5. rpf3 receive pool full - hdlc channel 3 32 bytes of a frame have arrived in the receive fifo3. the frame is not yet completely received. falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 455 ds1.1, 2003-10-23 hardware description global interrupt status register (read) value after reset: 00 h plll system pll lock status 0 = pll is unlocked. 1 = pll is locked. isr5 pending interrupt(s) in interrupt status register 5 0 = no pending interrupt. 1 = at least one interrupt is pending. isr4 pending interrupt(s) in interrupt status register 4 0 = no pending interrupt. 1 = at least one interrupt is pending. isr3 pending interrupt(s) in interrupt status register 3 0 = no pending interrupt. 1 = at least one interrupt is pending. isr2 pending interrupt(s) in interrupt status register 2 0 = no pending interrupt. 1 = at least one interrupt is pending. isr1 pending interrupt(s) in interrupt status register 1 0 = no pending interrupt. 1 = at least one interrupt is pending. isr0 pending interrupt(s) in interrupt status register 0 0 = no pending interrupt. 1 = at least one interrupt is pending. 70 gis plllisr5isr4isr3isr2isr1isr0 (6e) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 456 ds1.1, 2003-10-23 hardware description receive signaling register (read) value after reset: not defined receive signaling register 1 to 12 each register contains the received bit robbing information for 8 ds0 channels. the received robbed bit signaling information of a complete esf multiframe is compared to the previously received one. in f12/72 frame format the received signaling information of every 24 frames is compared to the previously received 24 frames. if the contents changed a receive signaling changed interrupt isr0.rsc is generated and informs the user that a new multiframe has to be read within the next 3 ms. received data is stored in rs(12:1) registers. the rs1.7 is received in channel 1 frame 1 and rs12.0 in channel 24 frame 24 (esf). if requests for reading the rs(12:1) registers are ignored, received data might get lost. additionally a receive signaling data change pointer indicates an update of register rs(12:1). refer also to register rsp(2:1). access to rs(12:1) registers is only valid if the serial receive signaling access on the system highway is disabled. table 74 receive signaling registers (t1/j1) 70 rs1 a1 b1 c1/a2 d1/b2 a2/a3 b2/b3 c2/a4 d2/b4 (70) rs2 a3/a5 b3/b5 c3/a6 d3/b6 a4/a7 b4/b7 c4/a8 d4/b8 (71) rs3 a5/a9 b5/b9 c5/a10 d5/b10 a6/a11 b6/b11 c6/a12 d6/b12 (72) rs4 a7/a13 b7/b13 c7/a14 d7/b14 a8/a15 b8/b15 c8/a16 d8/b16 (73) rs5 a9/a17 b9/b17 c9/a18 d9/b18 a10/a19 b10/b19 c10/a20 d10/b20 (74) rs6 a11/a21 b11/b21 c11/a22 d11/b22 a12/a23 b12/b23 c12/a24 d12/b24 (75) rs7 a13/a1 b13/b1 c13/a2 d13/b2 a14/a3 b14/b3 c14/a4 d14/b4 (76) rs8 a15/a5 b15/b5 c15/a6 d15/b6 a16/a7 b16/b7 c16/a8 d16/b8 (77) rs9 a17/a9 b17/b9 c17/a10 d17/b10 a18/a11 b18/b11 c18/a12 d18/b12 (78) rs10 a19/a13 b19/b13 c19/a14 d19/b14 a20/a15 b20/b15 c20/a16 d20/b16 (79) rs11 a21/a17 b21/b17 c21/a18 d21/b18 a22/a19 b22/b19 c22/a20 d22/b20 (7a) rs12 a23/a21 b23/b21 c23/a22 d23/b22 a24/a23 b24/b23 c24/a24 d24/b24 (7b) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 457 ds1.1, 2003-10-23 hardware description receive byte count register 2 (read) value after reset: 00 h ov2 counter overflow - hdlc channel 2 0 = less than or equal to 128 bytes received 1 = more than 128 bytes received rbc2(6:0) receive byte count - hdlc channel 2 indicates the length of a received frame. receive byte count register 3 (read) value after reset: 00 h ov3 counter overflow - hdlc channel 3 0 = less than or equal to 128 bytes received 1 = more than 128 bytes received rbc3(6:0) receive byte count - hdlc channel 3 indicates the length of a received frame. signaling status register 2 (read) value after reset: 00 h xdov2 transmit data overflow - hdlc channel 2 more than 32 bytes have been written to the xfifo2. this bit is reset ? by a transmitter reset command xres or ? when all bytes in the accessible half of the xfifo2 have been moved in the inaccessible half. 70 rbc2 ov2 rbc26 rbc25 rbc24 rbc23 rbc22 rbc21 rbc20 (90) 70 rbc3 ov3 rbc36 rbc35 rbc34 rbc33 rbc32 rbc31 rbc30 (91) 70 sis2 xdov2 xfw2 xrep2 rli2 cec2 (a9) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 458 ds1.1, 2003-10-23 hardware description xfw2 transmit fifo write enable - hdlc channel 2 data can be written to the xfifo2. xrep2 transmission repeat - hdlc channel 2 status indication of cmdr2.xrep2. rli2 receive line inactive - hdlc channel 2 neither flags as interframe time fill nor frames are received via the signaling time slot. cec2 command executing - hdlc channel 2 0 = no command is currently executed, the cmdr3 register can be written to. 1 = a command (written previously to cmdr3) is currently executed, no further command can be temporarily written in cmdr3 register. note:cec2 will be active up to 2.5 periods of the current system data rate. receive signaling status register 2 (read) value after reset: 00 h rsis2 relates to the last received hdlc channel 2 frame; it is copied into rfifo2 when end-of-frame is recognized (last byte of each stored frame). vfr2 valid frame - hdlc channel 2 determines whether a valid frame has been received. 1 = valid 0 = invalid an invalid frame is either ? a frame which is not an integer number of 8 bits (n 8 bits) in length (e.g. 25 bits), or ? a frame which is too short taking into account the operation mode selected via mode2 (mds2(2:0)) and the selection of receive crc on/off (ccr3.rcrc2) as follows: mds2(2:0) = 011 (16 bit address), rcrc2=0 : 4 bytes; rcrc2=1 : 3 or 4 bytes 70 rsis2 vfr2 rdo2 crc162 rab2 ha12 ha02 la2 (aa) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 459 ds1.1, 2003-10-23 hardware description mds2(2:0) = 010 (8 bit address), rcrc2=0 : 3 bytes; rcrc2=1 : 2 or 3 bytes note:shorter frames are not reported. rdo2 receive data overflow - hdlc channel 2 a data overflow has occurred during reception of the frame. additionally, an interrupt can be generated (refer to isr4.rdo2/imr4.rdo2). crc162 crc16 compare/check - hdlc channel 2 0 = crc check failed; received frame contains errors. 1 = crc check o.k.; received frame is error-free. rab2 receive message aborted - hdlc channel 2 this bit is set, if more than 5 contiguous 1-bits are detected. ha12, ha02 high byte address compare - hdlc channel 2 significant only if 2-byte address mode is selected. in operating modes which provide high byte address recognition, the falc ? compares the high byte of a 2-byte address with the contents of two individually programmable registers (rah1, rah2) and the fixed values fe h and fc h (broadcast address). depending on the result of this comparison, the following bit combinations are possible: 00 = rah2 has been recognized 01 = broadcast address has been recognized 10 = rah1 has been recognized c/r=0 (bit 1) 11 = rah1 has been recognized c/r=1 (bit 1) note:if rah1, rah2 contain identical values, a match is indicated by "10" or "11". falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 460 ds1.1, 2003-10-23 hardware description la2 low byte address compare - hdlc channel 2 significant in hdlc modes only. the low byte address of a 2-byte address field, or the single address byte of a 1-byte address field is compared with two registers. (ral1, ral2). 0 = ral2 has been recognized 1 = ral1 has been recognized signaling status register 3 (read) value after reset: 00 h xdov3 transmit data overflow - hdlc channel 3 more than 32 bytes have been written to the xfifo3. this bit is reset ? by a transmitter reset command xres or ? when all bytes in the accessible half of the xfifo3 have been moved in the inaccessible half. xfw3 transmit fifo write enable - hdlc channel 3 data can be written to the xfifo3. xrep3 transmission repeat - hdlc channel 3 status indication of cmdr3.xrep3. rli3 receive line inactive - hdlc channel 3 neither flags as interframe time fill nor frames are received via the signaling time slot. cec3 command executing - hdlc channel 3 0 = no command is currently executed, the cmdr4 register can be written to. 1 = a command (written previously to cmdr4) is currently executed, no further command can be temporarily written in cmdr4 register. note: cec3 will be active at most 2.5 periods of the current system data rate. 70 sis3 xdov3 xfw3 xrep3 rli3 cec3 (9a) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 461 ds1.1, 2003-10-23 hardware description receive signaling status register 3 (read) value after reset: 00 h rsis3 relates to the last received hdlc channel 3 frame; it is copied into rfifo3 when end-of-frame is recognized (last byte of each stored frame). vfr3 valid frame - hdlc channel 3 determines whether a valid frame has been received. 1 = valid 0 = invalid an invalid frame is either ? a frame which is not an integer number of 8 bits (n 8 bits) in length (e.g. 25 bits), or ? a frame which is too short taking into account the operation mode selected via mode3 (mds3(2:0)) and the selection of receive crc on/off (ccr4.rcrc3) as follows: mds3(2:0)=011 (16 bit address), rcrc3=0: 4 bytes; rcrc3=1: 3 or 4 bytes mds3(2:0)=010 (8 bit address), rcrc3=0: 3 bytes; rcrc3=1: 2 or 3 bytes note:shorter frames are not reported. rdo3 receive data overflow - hdlc channel 3 a data overflow has occurred during reception of the frame. additionally, an interrupt can be generated (refer to isr5.rdo3/imr5.rdo3). crc163 crc16 compare/check - hdlc channel 3 0 = crc check failed; received frame contains errors. 1 = crc check o.k.; received frame is error-free. rab3 receive message aborted - hdlc channel 3 this bit is set, if more than 5 contiguous 1-bits are detected. 70 rsis3 vfr3 rdo3 crc163 rab3 ha13 ha03 la3 (9b) falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 462 ds1.1, 2003-10-23 hardware description ha13, ha03 high byte address compare - hdlc channel 3 significant only if 2-byte address mode is selected. in operating modes which provide high byte address recognition, the falc ? compares the high byte of a 2-byte address with the contents of two individually programmable registers (rah1, rah2) and the fixed values fe h and fc h (broadcast address). depending on the result of this comparison, the following bit combinations are possible: 00 = rah2 has been recognized 01 = broadcast address has been recognized 10 = rah1 has been recognized c/r=0 (bit 1) 11 = rah1 has been recognized c/r=1 (bit 1) note:if rah1, rah2 contain identical values, a match is indicated by "10" or "11". la3 low byte address compare - hdlc channel 3 significant in hdlc modes only. the low byte address of a 2-byte address field, or the single address byte of a 1-byte address field is compared with two registers. (ral1, ral2). 0 = ral2 has been recognized 1 = ral1 has been recognized falc ? 56 pef 2256 h/e t1/j1 registers user?s manual 463 ds1.1, 2003-10-23 hardware description receive fifo 2 (read) value after reset: 00 h rf(15:0) receive fifo - hdlc channel 2 the function is equivalent to rfifo of hdlc channel 1. receive fifo 3 (read) value after reset: 00 h rf(15:0) receive fifo - hdlc channel 3 the function is equivalent to rfifo of hdlc channel 1. multifunction port input status register (read) value after reset: xx h rpd port rpd input status rpc port rpc input status rpb port rpb input status rpa port rpa input status xpd port xpd input status xpc port xpc input status xpb port xpb input status xpa port xpa input status 70 rfifo2 rf7 rf0 (9c) rfifo2 rf15 rf8 (9d) 70 rfifo3 rf7 rf0 (9e) rfifo3 rf15 rf8 (9f) 70 mfpi rpd rpc rpb rpa xpd xpc xpb xpa (ab) falc ? 56 pef 2256 h/e electrical characteristics user?s manual 464 ds1.1, 2003-10-23 hardware description 11 electrical characteristics this chapter describes operating conditions, dc and ac characteristics and limits. 11.1 absolute maximum ratings table 75 defines the maximum voltages and temperature which may be applied to the device without damage. table 75 absolute maximum ratings parameter symbol values unit note/test condition min. typ. max. ambient temperature under bias t a -40 ? +85 c? storage temperature t stg -65 ? +125 c? moisture level 3 temperature t ml3 ??+225 c according to ips j-std 020 +245 c according to ifx internal standard supply voltage (pads, digital) v dd -0.5 3.30 4.50 v ? supply voltage (core, digital) v ddc -0.5 1.80 2.40 v ? supply voltage (pll, analog) v ddp -0.5 3.30 4.50 v ? supply voltage (receiver, analog) v ddr -0.5 3.30 4.50 v ? supply voltage (transmitter, analog) v ddx -0.5 3.30 4.50 v ? receiver input signal v rlmax -0.8 ? 4.50 v rl1/rl2 voltage on any pin v max -0.5 ? 4.50 v except v ddc , rl1/rl2 falc ? 56 pef 2256 h/e electrical characteristics user?s manual 465 ds1.1, 2003-10-23 hardware description attention: if the 1.8 v power supply is externally driven on v ddc , the voltage on this pin must never exceed the 3.3 v supply voltages on pins v dd , v ddp , v ddx and v ddr , even during power up and power down of the circuit. attention: absolute maximum ratings are stress ratings only, and functional operation and reliability under conditions beyond those defined in the normal operating conditions is not guaranteed. stresses above the maximum ratings are likely to cause permanent damage to the chip. 11.2 operating range table 76 defines the maximum voltages and temperature which may be applied to guarantee proper operation. esd robustness hbm v esd,hbm ? ? 2000 v 1.5 k ? , 100 pf; according to eia/ jesd22-a114-b esd robustness cdm v esd,cdm ? ? 500 v according to esd association standard ds5.3.1 - 1999 table 76 operating range parameter symbol values unit note/test condition min. typ. max. ambient temperature t a -40 ? +85 c? supply voltage (pads, digital) v dd 3.13 3.30 3.46 v 3.3 v 5% supply voltage (core, digital) v ddc 1.62 1.80 1.98 v 1.8 v 10% supply voltage (pll, analog) v ddp 3.13 3.30 3.46 v 3.3 v 5% supply voltage (receiver, analog) v ddr 3.13 3.30 3.46 v 3.3 v 5% 1) supply voltage (transmitter, analog) v ddx 3.13 3.30 3.46 v 3.3 v 5% table 75 absolute maximum ratings (cont?d) parameter symbol values unit note/test condition min. typ. max. falc ? 56 pef 2256 h/e electrical characteristics user?s manual 466 ds1.1, 2003-10-23 hardware description note: v dd , v ddr and v ddx have to be connected to the same voltage level. 11.3 dc characteristics analog input voltages on rl1/2 v ia 0?3.60v digital input voltages v id 0?3.60v ground v ss 000v 1) voltage ripple on analog supply less than 50 mv table 77 dc characteristics parameter symbol values unit note/test condition min. typ. max. input low voltage v il ? 0.4 ? 0.8 v 1) input high voltage v ih 2.0 ? 3.46 v 1) output low voltage v ol v ss ?0.45v i ol =+ 2ma 2) output high voltage v oh 2.4 ? v dd v i oh =- 2ma 2) average power supply current (analog line interface mode, single power supply) i dde1 ? 80 145 ma e1 application 3) lim1.drs = 0 b vsel = 1 b i ddt1 ? 80 145 ma t1 application 4) lim1.drs = 0 b vsel = 1 b average power supply current (digital line interface mode, single power supply) i dd ?5090malim1.drs=1 b 5) vsel = 1 b input leakage current i l11 ??1 a v in =v dd 6) input leakage current i il12 ??1 a v in =v ss 6) input pullup current i p 2?15 a v in =v ss table 76 operating range (cont?d) parameter symbol values unit note/test condition min. typ. max. falc ? 56 pef 2256 h/e electrical characteristics user?s manual 467 ds1.1, 2003-10-23 hardware description output leakage current i oz1 ??1 a v out = tristate v ss < v meas < v dd measured against v dd and v ss ; all except xl1/2 transmitter leakage current i tl ??15 axl1/2= v ddx ; xpm2.xlt = 1 ??15 axl1/2= v ssx ; xpm2.xlt = 1 transmitter output impedance r x ??3 ? applies to xl1and xl2 7) transmitter output current i x ? ? 105 ma xl1, xl2 differential peak voltage of a mark v x ? ? 2.15 v voltage between xl1 and xl2 receiver peak voltage of a mark v r12 ? ? 3.8 v rz signals only ? ? 4.1 v rz signals, during t1 pulse over-/undershoot only receiver differential peak voltage of a mark (between rl1 and rl2) v r ? ? 4.00 v rz signals only ? ? 4.63 v rz signals, during t1 pulse over-/undershoot only receiver input impedance z r ?50?k ? 7) receiver internal termination resistor r r 255 300 345 ? internal termination enabled table 77 dc characteristics (cont?d) parameter symbol values unit note/test condition min. typ. max. falc ? 56 pef 2256 h/e electrical characteristics user?s manual 468 ds1.1, 2003-10-23 hardware description note: typical characteristics specify mean values expected over the production spread. if not specified otherwise, typical characteristics apply at t a = 25 c and 3.3 v supply voltage. receiver sensitivity s rlh 0?43dbrl1, rl2 e1 mode 0?36 rl1, rl2 t1 mode analog switch resistance r as 2.7 7.2 11.7 ? switch closed 100 ? ? k ? switch open analog switch current i as -2 ? 2 ma dc -40 40 ma ac 1) applies to all input pins except analog pins rlx 2) applies to all output pins except pins xlx 3) wiring conditions and external circuit configuration according to figure 112 and table 101 on page 497 . 4) wiring conditions and external circuit configuration according to figure 112 and table 102 on page 498 . 5) system interface at 16 mhz; all-ones data. 6) pin leakage is measured in a test mode with all internal pullups disabled. 7) parameter not tested in production table 77 dc characteristics (cont?d) parameter symbol values unit note/test condition min. typ. max. falc ? 56 pef 2256 h/e electrical characteristics user?s manual 469 ds1.1, 2003-10-23 hardware description 11.4 ac characteristics 11.4.1 master clock timing figure 85 mclk timing table 78 mclk timing parameters parameter symbol values unit note/test condition min. typ. max. clock period of mclk 1 50 ? 980.4 ns high phase of mclk 2 40 ? ? % low phase of mclk 3 40 ? ? % clock accuracy 32 1) 1) if clock divider programming fits without rounding. ?28 2) 2) if clock divider programming requires rounding. ppm f0007 mclk 1 2 3 falc ? 56 pef 2256 h/e electrical characteristics user?s manual 470 ds1.1, 2003-10-23 hardware description 11.4.2 jtag boundary scan interface figure 86 jtag boundary scan timing table 79 boundary scan timing parameter values parameter symbol values unit note/test condition min. typ. max. trs reset active low time 1 200 ? ? ns tck period 2 250 ? ? ns tck high time 3 80 ? ? ns tck low time 4 80 ? ? ns tms, tdi setup time 5 40 ? ? ns tms, tdi hold time 6 40 ? ? ns tdati setup time 7 40 ? ? ns tdati hold time 8 40 ? ? ns tdo, tdato output delay 9 ? ? 100 ns f0120 tck tms, tdi tdati tdo, tdato trs 1 3 4 5 6 2 7 8 9 falc ? 56 pef 2256 h/e electrical characteristics user?s manual 471 ds1.1, 2003-10-23 hardware description 11.4.3 reset figure 87 reset timing 11.4.4 microprocessor interface 11.4.4.1 intel bus interface mode figure 88 intel non-multiplexed address timing table 80 reset timing parameter values parameter symbol values unit note/test condition min. typ. max. res pulse width low 1 10 1) 1) while mclk is running ??s f0008 res 1 wr rd cs bhe ax 1 3 3a 2 itt10975 falc ? 56 pef 2256 h/e electrical characteristics user?s manual 472 ds1.1, 2003-10-23 hardware description figure 89 intel multiplexed address timing figure 90 intel read cycle timing wr rd 3 cs ale bhe ax 4 6 1 7 5 3a itt10977 7a f0121 cs rd wr dx 8 9 8 9 10 11 falc ? 56 pef 2256 h/e electrical characteristics user?s manual 473 ds1.1, 2003-10-23 hardware description figure 91 intel write cycle timing d8) d7 d0 ... (d15... 16 itt06471 wr rd cs 15 13 14 12 8 9 9 falc ? 56 pef 2256 h/e electrical characteristics user?s manual 474 ds1.1, 2003-10-23 hardware description table 81 intel bus interface timing parameter values parameter symbol values unit note/test condition min. typ. max. address, bhe setup time 1 5??ns address, bhe hold time 2 2 ? ? ns cs setup time 3 0 ? ? ns cs hold time 3a 0 ? ? ns address, bhe stable before ale inactive 420??ns address, bhe hold after ale inactive 510??ns ale pulse width 6 30 ? ? ns ale setup time before command active 7 0??ns ale to command inactive delay 7a 30 ? ? ns rd , wr pulse width 8 80 ? ? ns rd , wr control interval 9 70 ? ? ns data valid after rd active 10 ??75ns data hold after rd inactive 11 0?30ns data stable before wr inactive 15 30 ? ? ns data hold after wr inactive 16 10 ? ? ns falc ? 56 pef 2256 h/e electrical characteristics user?s manual 475 ds1.1, 2003-10-23 hardware description 11.4.4.2 motorola bus interface mode figure 92 motorola read cycle timing figure 93 motorola write cycle timing f0122 cs ax, ble 17 ds rw dx 18 22 19 19a 20 21 23 24 25 ds ... d0 (d15 d7... d8) 26 rw cs ax ble 20 19 17 22a 27 itt10974 21 19a 18 23 falc ? 56 pef 2256 h/e electrical characteristics user?s manual 476 ds1.1, 2003-10-23 hardware description table 82 motorola bus interface timing parameter values parameter symbol values unit note/test condition min. typ. max. address, ble setup time before ds active 17 15 ? ? ns address, ble hold after ds inactive 18 2 ? ? ns cs active before ds active 19 0 ? ? ns cs hold after ds inactive 19a 0 ? ? ns rw stable before ds active 20 10 ? ? ns rw hold after ds inactive 21 0 ? ? ns ds pulse width 22 80 ? ? ns read access ds pulse width 22a 70 ? ? ns write access ds control interval 23 70 ? ? ns data valid after ds active 24 ? ? 75 ns read access data hold after ds inactive 25 10 ? 30 ns read access data stable before ds active 26 30 ? ? ns write access data hold after ds inactive 27 10 ? ? ns write access falc ? 56 pef 2256 h/e electrical characteristics user?s manual 477 ds1.1, 2003-10-23 hardware description 11.4.5 line interface figure 94 digital line interface receive timing figure 95 digital line interface transmit timing f0264_1 rclki roid 30 32 31 34 33 rdip rdin 30a f0264_2 xclk 1) cmi coding 35 37 36 38 38 xoid xdop xdon xfm xoid 1) falc ? 56 pef 2256 h/e electrical characteristics user?s manual 478 ds1.1, 2003-10-23 hardware description table 83 digital line interface timing parameter values parameter symbol values unit note/test condition min. typ. max. e1 mode rclki clock period 30 ? 488 ? ns rdip/rdin period high 30a 122 244 366 ns rclki clock period low 31 180 ? ? ns rclki clock period high 32 180 ? ? ns roid setup 33 50 ? ? ns roid hold 34 50 ? ? ns xclk clock period 35 ? 488 ? ns xclk clock period low 36 190 ? ? ns 150 ? ? ns lim1.jatt = 0 lim1.rl = 1 xclk clock period high 37 190 ? ? ns 150 ? ? ns lim1.jatt = 0 lim1.rl = 1 xoid delay 38 ? ? 60 ns nrz coding xdop/xdon delay ? ? 60 ns hdb3/ami/b8zs coding t1/j1 mode rclki clock period 30 ? 648 ? ns rdip/rdin period high 30a 162 324 486 ns rclki clock period low 31 240 ? ? ns rclki clock period high 32 240 ? ? ns roid setup 33 50 ? ? ns roid hold 34 50 ? ? ns xclk clock period 35 ? 648 ? ns xclk clock period low 36 230 ? ? ns 200 ? ? ns lim1.jatt = 0 lim1.rl = 1 falc ? 56 pef 2256 h/e electrical characteristics user?s manual 479 ds1.1, 2003-10-23 hardware description xclk clock period high 37 230 ? ? ns 200 ? ? ns lim1.jatt = 0 lim1.rl = 1 xoid delay 38 ? ? 60 ns nrz coding xdop/xdon delay ? ? 60 ns hdb3/ami/b8zs coding table 83 digital line interface timing parameter values (cont?d) parameter symbol values unit note/test condition min. typ. max. falc ? 56 pef 2256 h/e electrical characteristics user?s manual 480 ds1.1, 2003-10-23 hardware description 11.4.6 system interface figure 96 rclk and rfsp output timing note: the active edge can be programmed to be positive (rising) or negative (falling). only negative edge timing is shown in figure 96 . this timing is valid only, if rclk is derived from dpll and not, if rclk is jitter attenuated. table 84 rclk and rfsp timing parameter values parameter symbol values unit note/test condition min. typ. max. rclk period e1 1 ? 488 ? ns 2.048 mhz rclk period e1 ? 122 ? ns 2.048 mhz 4 rclk period t1/j1 ? 648 ? ns 1.544 mhz rclk period t1/j1 ? 162 ? ns 1.544 mhz 4 rclk pulse high 2 40 ? 60 % rclk pulse low 3 40 ? 60 % rfsp delay 4 ? ? 80 ns f56v2_timing_rfsp_1 dat a valid rclk rfsp (out put) 1 2 3 4 falc ? 56 pef 2256 h/e electrical characteristics user?s manual 481 ds1.1, 2003-10-23 hardware description figure 97 sclkr/sclkx input timing table 85 sclkr/sclkx timing parameter values parameter symbol values unit note/test condition min. typ. max. sclkr/sclkx period 1 ? 61 ? ns 16.384 mhz ?122?ns8.192mhz ?244?ns4.096mhz ?488?ns2.048mhz ? 81 ? ns 12.352 mhz ?162?ns6.176mhz ?324?ns3.088mhz ?648?ns1.544mhz sclkr/sclkx pulse high 240??% sclkr/sclkx pulse low 340??% f56v2_timing_sclkr_sclk x sclkr sclkx (input) 1 2 3 falc ? 56 pef 2256 h/e electrical characteristics user?s manual 482 ds1.1, 2003-10-23 hardware description figure 98 receive system interface marker timing table 86 receive system interface marker timing parameter values parameter symbol values unit note/test condition min. typ. max. sclkr input mode rdo delay 1 0 ? 35 ns rsigm, rmfb, dlr, rfm, freeze, rsig marker delay 2 0?45ns sclkr output mode rdo delay 1a 0 ? 20 ns rsigm, rmfb, dlr, rfm, freeze, rsig marker delay 2a 0?20ns f56v2_timing_rxmarker data valid sclkr 1 data valid rdo rsig rsigm dlr rfm rmfb freeze 1 2 2 positive edge timing 1) negative edge timing 1) 1) active edge can be programmed to be positive or negative falc ? 56 pef 2256 h/e electrical characteristics user?s manual 483 ds1.1, 2003-10-23 hardware description figure 99 sypr and sypx timing table 87 sypr and sypx timing parameter values parameter symbol values unit note/test condition min. typ. max. sclkr input mode sclkr period ( t 1 ) 1 61 ? 648 ns sypr /sypx inactive setup time 21 t 1 ??ns sypr /sypx setup time 3 5 ? ? ns sypr /sypx hold time 4 15 ? ? ns xmfs inactive setup time 51 t 1 ??ns xmfs setup time 6 5 ? ? ns xmfs hold time 7 15 ? ? ns sclkr output mode sclkr period ( t 1 ) 1a 61 ? 648 ns sypr /sypx inactive setup time 2a 1 t 1 ??ns f5 6 v2_ timin g _sypr_ sypx sclkr sclkx 1 2 3 4 inactive active low sypr sypx 5 6 7 inactive active low xmfs active edge falc ? 56 pef 2256 h/e electrical characteristics user?s manual 484 ds1.1, 2003-10-23 hardware description sypr /sypx setup time 3a 25 ? ? ns sypr /sypx hold time 4a 0 ? ? ns xmfs inactive setup time 5a 1 t 1 ??ns xmfs setup time 6a 25 ? ? ns xmfs hold time 7a 0 ? ? ns table 87 sypr and sypx timing parameter values (cont?d) parameter symbol values unit note/test condition min. typ. max. falc ? 56 pef 2256 h/e electrical characteristics user?s manual 485 ds1.1, 2003-10-23 hardware description figure 100 transmit system interface marker timing table 88 transmit system interface marker timing parameter values parameter symbol values unit note/test condition min. typ. max. sclkr input mode 1) 1) parameters are based on sclkr when cmr2.ixsc = 1 and on sclkx when cmr2.ixsc = 0. xmfb, dlx, xsigm delay 1 ? ? 100 ns sclkr output mode xmfb, dlx, xsigm delay 1 ? ? -20 ns f56v2_timing_txmarker sclkr sclkx 1 xmfb dlx xsigm active edge 1) 1) active edge can be programmed to be positive or negative falc ? 56 pef 2256 h/e electrical characteristics user?s manual 486 ds1.1, 2003-10-23 hardware description figure 101 xdi and xsig timing table 89 xdi and xsig timing parameter values parameter symbol values unit note/test condition min. typ. max. sclkr input mode 1) 1) parameters are based on sclkr when cmr2.ixsc = 1 and on sclkx when cmr2.ixsc = 0. xdi setup time 1 5 ? ? ns xdi hold time 2 15 ? ? ns xsig setup time 3 5 ? ? ns xsig hold time 4 15 ? ? ns sclkr output mode xdi setup time 1a 25 ? ? ns xdi hold time 2a 20 ? ? ns xsig setup time 3a 25 ? ? ns xsig hold time 4a 20 ? ? ns f56v2_timing_xdi_xsig sclkr sclkx 1 xdi active edge 1) 1) active edge can be programmed to be positive or negative 2 3 xsig 4 falc ? 56 pef 2256 h/e electrical characteristics user?s manual 487 ds1.1, 2003-10-23 hardware description figure 102 tclk input timing table 90 tclk timing parameter values parameter symbol values unit note/test condition min. typ. max. tclk period e1 1 ? 488 ? ns 2.048 mhz tclk period e1 (2.048 mhz 4) ? 122 ? ns 2.048 mhz 4 tclk period t1/j1 ? 648 ? ns 1.544 mhz tclk period t1/j1 ? 162 ? ns 1.544 mhz 4 tclk high 2 40 ? ? % tclk low 3 40 ? ? % f56v2_timing_tcl k tclk 1 2 3 falc ? 56 pef 2256 h/e electrical characteristics user?s manual 488 ds1.1, 2003-10-23 hardware description figure 103 xclk timing table 91 xclk timing parameter values parameter symbol values unit note/test condition min. typ. max. xclk delay 1) 1) valid in transmit buffer bypass mode only 1 ? ? 100 ns e1 mode ? ? 100 ns t1/j1 mode f56v2_timing_xcl k mclk 1 xclk falc ? 56 pef 2256 h/e electrical characteristics user?s manual 489 ds1.1, 2003-10-23 hardware description figure 104 sec timing table 92 sec timing parameter values parameter symbol values unit note/test condition min. typ. max. sec input period 1 ? 1 ? s e1/t1/j1 sec input high 2 976 ? ? ns e1 1296 ? ? ns t1/j1 sec input low 3 976 ? ? ns e1 1296 ? ? ns t1/j1 sec output period 4 ? 1 ? s e1/t1/j1 sec high output 5 976 ? ? ns e1 1296 ? ? ns t1/j1 f56v2_timing_sec 1 sec (input) 1) clock running continuously 2 3 4 sec 1) (output) 5 6 falc ? 56 pef 2256 h/e electrical characteristics user?s manual 490 ds1.1, 2003-10-23 hardware description figure 105 fsc timing table 93 fsc timing parameter values parameter symbol values unit note/test condition min. typ. max. fsc 1) period 1) fsc can be programmed to be active high or active low (only the active low timing diagram is shown here) 1?125? s fsc high/low active time 2?488?nse1 ? 648 ? ns t1/j1 rclk to fsc delay 3 ? 50 80 ns sclkr to fsc delay 4 ? 50 80 ns f56v2_timing_fsc rclk sclkr (out put ) 3 4 2 1 fsc falc ? 56 pef 2256 h/e electrical characteristics user?s manual 491 ds1.1, 2003-10-23 hardware description figure 106 sync timing table 94 sync timing parameter values parameter symbol values unit note/test condition min. typ. max. sync high time 1 30 ? ? % sync low time 2 30 ? ? % f56v2_timing_sync sync 1 2 falc ? 56 pef 2256 h/e electrical characteristics user?s manual 492 ds1.1, 2003-10-23 hardware description 11.4.7 pulse templates - transmitter 11.4.7.1 pulse template e1 data interface figure 107 e1 pulse shape at transmitter output table 95 e1 pulse amplitude values parameter symbol values unit note/test condition min. typ. max. nominal pulse amplitude v 2.70 3.00 3.30 v 120 ? 2.13 2.37 2.60 v 75 ? itd00573 10 % 10 % % 10 10 % % 10 10 % 20 % 269 ns (244 + 25) (244 - 50) ns 194 219 ns (244 - 25) ns 244 (244 + 244) ns 488 % 0 50 % % v =100 nominal pulse % 20 20 % falc ? 56 pef 2256 h/e electrical characteristics user?s manual 493 ds1.1, 2003-10-23 hardware description 11.4.7.2 pulse template e1 synchronization interface figure 108 dcim clock pulse shape at transmitter output table 96 dcim pulse output amplitude values parameter symbol values unit note/test condition min. typ. max. pulse maximum peak value v 1.90 v 120 ? 1.50 v 75 ? pulse minimum peak value v 1 0.75 v 120 ? 1.50 v 75 ? clock period t 488 ns 50 ppm f56v2_pulse_template_dci m t 30 t 4 t 4 t 4 t 4 t +v +v 1 ?v 0 t1818900-92 ?v 1 t 30 t 30 t 30 t 30 t 30 shaded area in which signal should be monotonic t average period of synchronizing signal falc ? 56 pef 2256 h/e electrical characteristics user?s manual 494 ds1.1, 2003-10-23 hardware description 11.4.7.3 pulse template t1 figure 109 t1 pulse shape at the cross connect point table 97 t1 pulse template at cross connect point (t1.102 1) ) 1) requirements of itu-t g.703 are also fulfilled maximum curve minimum curve time [ns] level [%] 2) 2) 100 % value must be in the range of 2.4 v and 3.6 v; tested at 0 ft. and 655 ft. using pic 22awg cable characteristics. time [ns] level [%] 0 50-5 250 5 350 -5 325 80 350 50 325 115 400 95 425 115 500 95 500 105 600 90 675 105 650 50 725 -7 650 -45 1100 5 800 -45 1250 5 925 -20 1100 -5 1250 -5 itd00574 % 100 = v 50 % 0 -50 % 0 250 500 750 1000 ns t normalized amplitude falc ? 56 pef 2256 h/e electrical characteristics user?s manual 495 ds1.1, 2003-10-23 hardware description 11.5 capacitances 11.6 package characteristics figure 110 thermal behavior of package table 98 capacitance values parameter symbol values unit note/test condition min. typ. max. input capacitance 1) c in 5?10pf output capacitance 1) c out 8 ? 15 pf all except xl1/2 output capacitance 1) c out 8?20pfxl1/2 table 99 package characteristic values parameter symbol values unit note/test condition min. typ. max. thermal resistance mqfp r thjam 1) 1) r thja = (t junction - t ambient )/power (not tested in production) ? 47 ? k/w single layer pcb, no convection r thjc 2) 2) r thjc = (t junction - t case )/power (not tested in production) ?9?k/w thermal resistance bga r thjab 1) ? 29 ? k/w single layer pcb, natural convection junction temperature r j ? ? 125 c f0051 falc ? 56 pef 2256 h/e electrical characteristics user?s manual 496 ds1.1, 2003-10-23 hardware description 11.7 test configuration 11.7.1 ac tests figure 111 input/output waveforms for ac testing table 100 ac test conditions parameter symbol values unit note/test condition min. typ. max. load capacitance c l ?50?pf input voltage high v ih ? 2.4 ? v all except rl1/2 input voltage low v il ? 0.4 ? v all except rl1/2 test voltage high v th ? 2.0 ? v all except xl1/2 test voltage low v tl ? 0.8 ? v all except xl1/2 tim ing test points v th v tl device under test c l test levels v ih v il drive levels f0067 falc ? 56 pef 2256 h/e electrical characteristics user?s manual 497 ds1.1, 2003-10-23 hardware description 11.7.2 power supply test figure 112 device configuration for power supply testing table 101 power supply test conditions e1 parameter symbol values unit note/test condition min. typ. max. load resistance r 1 4 ? 1% termination resistance r 2 120 ? 1% line impedance r l 120 ? line length l 0.2 m transformer ratio transmit t t1 : t t2 2.4 transformer ratio receive t r1 : t r2 1 pcm highway frequency sclkx sclkr 2.048 mhz test signal 2 15 -1 prbs pattern f017 6 falc ? 56 r 1 r 2 system interface v ddx v ddr v dd t t1 : t t2 t r1 : t r2 r l r 1 falc ? 56 pef 2256 h/e electrical characteristics user?s manual 498 ds1.1, 2003-10-23 hardware description pulse mask programming xpm2 00 h xpm1 03 h xpm0 9c h ambient temperature t a 85 c table 102 power supply test conditions t1/j1 parameter symbol values unit note/test condition min. typ. max. load resistance r 1 4 ? 1% termination resistance r 2 100 ? 1% line impedance r l 100 ? line length l 0.2 m transformer ratio transmit t t1 : t t2 2.4 transformer ratio receive t r1 : t r2 1 pcm highway frequency sclkx sclkr 1.544 mhz test signal 2 15 -1 prbs pattern pulse mask programming xpm2 01 h xpm1 16 h xpm0 95 h ambient temperature t a 85 c table 101 power supply test conditions e1 (cont?d) parameter symbol values unit note/test condition min. typ. max. falc ? 56 pef 2256 h/e package outlines user?s manual 499 ds1.1, 2003-10-23 hardware description 12 package outlines figure 113 p-mqfp-80-1 (plastic metric quad flat package) gpm05249 smd = surface mounted device dimensions in mm you can find all of our packages, sorts of packing and others in our infineon internet page ?products?: http://www.infineon.com/products . falc ? 56 pef 2256 h/e package outlines user?s manual 500 ds1.1, 2003-10-23 hardware description figure 114 p-lbga-81-1 (plastic ball grid array package) lbga811 smd = surface mounted device dimensions in mm you can find all of our packages, sorts of packing and others in our infineon internet page ?products?: http://www.infineon.com/products . falc ? 56 pef 2256 h/e appendix user?s manual 501 ds1.1, 2003-10-23 hardware description 13 appendix 13.1 protection circuitry the design in figure 115 shows an example of how to build up a generic e1/t1/j1 platform. the circuit shown has been successfully checked against itu-t k.20 and k.21 lightning surge tests (basic level). figure 115 protection circuitry examples 13.2 application notes several application notes and technical documentation provide additional information. online access to supporting information is available on the internet page: http://www.infineon.com/falc on the same page you find as well the boundary scan file for falc ? 56 version 2.1 (bsdl file) 13.3 software support the following software package is provided together with the falc ? 56 reference system easy 2256: e1 and t1 driver functions supporting different etsi, at&t and telcordia (former: bellcore) requirements f0262_2 fuse 1.25 a r2 r3 r3 rj45 falc ? rl1 rl2 xl1 xl2 r1 r1 1:1 1:2.4 v dd v ss v dd v ss fuse 1.25 a fuse 1.25 a fuse 1.25 a a a b a a b a smp 100lc-35 (~65 pf) b smp p3500sc (~60 pf) ptc ptc ptc ptc falc ? 56 pef 2256 h/e appendix user?s manual 502 ds1.1, 2003-10-23 hardware description ibis model for falc ? 56 version 2.1 (according to ansi/eia-656) flexible master clock calculator external line front end calculator to make system design easier, two software tools are available. the first is the "master clock frequency calculator", which calculates the required register settings depending on the external master clock frequency (mclk). the second is the "external line front end calculator" which provides an easy method to optimize the external components depending on the selected application type. calculation results are traced an can be stored in a file or printed out for documentation. the tools run under a win9x/nt environment. screenshots of both programs are shown in figure 116 and figure 117 below. falc ? 56 pef 2256 h/e appendix user?s manual 503 ds1.1, 2003-10-23 hardware description figure 116 master clock frequency calculator flexible_master_clock_calc falc ? 56 pef 2256 h/e appendix user?s manual 504 ds1.1, 2003-10-23 hardware description figure 117 external line frontend calculator f0198_2256 falc ? 56 pef 2256 h/e user?s manual 505 ds1.1, 2003-10-23 hardware description terminology a a/d analog to digital adc analog to digital converter agc automatic gain control ais alarm indication signal (blue alarm) alos analog loss of signal ami alternate mark inversion ansi american national standards institute atm asynchronous transfer mode auxp auxiliary pattern b b8zs line coding to avoid too long strings of consecutive "0" bellcore bell communications research ber bit error rate bfa basic frame alignment bom bit orientated message bpv bipolar violation bsn backward sequence number c cas channel associated signaling cas-br channel associated signaling - bit robbing cas-cc channel associated signaling - common channel ccs common channel signaling cmi coded mark inversion code (also known as 1t2b code) cr command/response (special bit in ppr) crc cyclic redundancy check csu channel service unit cvc code violation counter d dco digitally controlled oscillator falc ? 56 pef 2256 h/e user?s manual 506 ds1.1, 2003-10-23 hardware description dl digital loop dpll digitally controlled phase locked loop ds1 digital signal level 1 e ea extended address (special bit in ppr) easy evaluation system for falc products eq equalizer esd electrostatic discharge esf extended superframe format (f24 format) etsi european telecommunication standards institute f falc ? framing and line interface component fas frame alignment sequence fcc us federal communication commission fcs frame check sequence (used in ppr) fisu fill in signaling unit fps framing pattern sequence fsn forward sequence number h hbm human body model for esd classification hdb3 high density bipolar of order 3 hdlc high level data link control i ibis i/o buffer information specification (ansi/eia-656) ibl in band loop (=llb) isdn integrated services digital network itu international telecommunications group j jatt jitter attenuator jtag joined test action group l lapd link access procedure on d-channel falc ? 56 pef 2256 h/e user?s manual 507 ds1.1, 2003-10-23 hardware description lbo line build out lcv line code violation lfa loss of frame alignment liu line interface unit ll local loop llb line loop back (= ibl) los loss of signal (red alarm) lsb least significant bit lssu link status signaling unit m mf multiframe msb most significant bit msu message signaling unit n nrz non return to zero signal p pdv pulse-density violation plb payload loop back pll phase locked loop pmqfp plastic metric quad flat pack (device package) ppr periodical performance report prbs pseudo random binary sequence ptqfp plastic thin metric quad flat pack (device package) r rai remote alarm indication (yellow alarm) rl remote loop s sapi service access point identifier (special octet in ppr) sf superframe sidactor overvoltage protection device for transmission lines t tap test access port (see ieee 1149) falc ? 56 pef 2256 h/e user?s manual 508 ds1.1, 2003-10-23 hardware description tei terminal endpoint identifier (special octet in ppr) u ui unit interval z zcs zero code suppression falc ? 56 pef 2256 h/e user?s manual 509 ds1.1, 2003-10-23 hardware description references this document refers to several international standards, listed in the following in alphabetical/numerical order. please note that some of the documents might still be under construction and not yet officially released. for updates, refer to the appropriate document sources. [1] american national standards institute (ansi), ansi ? t1.102-1993, "american national standard for telecommunications, digital hierarchy - electrical interfaces" [2] american national standards institute (ansi), ansi ? t1.403-1999, "american national standard for telecommunications, network and customer installation interfaces - ds1 electrical interface" [3] at&t, tr 54016, "data communications technical reference, requirements for interfacing digital terminal equipment to services employing the extended superframe format", september 1989 [4] at&t, tr 62411, "data communications technical reference, accunet? t1.5 service description and interface specification", december 1990 [5] at&t, tr 43801, "data communications technical reference, digital channel banks requirements and objectives", november 1982 [6] bell communications research, tr-tsy-000009, "asynchronous digital multiplexers, requirements and objectives", issue 1, may 1986. [7] electronic industries alliance (eia)/jedec solid state technology association, jesd22-a114-b, ?electrostatic discharge (esd) sensitivity testing human body model (hbm)?, june 2000 [8] european telecommunications standards institute, etsi en 300 011, "european telecommunication standard, integrated services digital network - primary rate user network interface", march 1998 [9] european telecommunications standards institute, etsi en 300 166, "european telecommunication standard, transmission and multiplexing - physical and electrical characteristics of hierarchical digital interfaces for equipment using the 2048 kbit/s - based plesiochronous or synchronous digital hierarchies", august 1993 falc ? 56 pef 2256 h/e user?s manual 510 ds1.1, 2003-10-23 hardware description [10] european telecommunications standards institute, etsi en 300 233, "european telecommunication standard, integrated services digital network - access digital section for isdn primary rate", may 1994 [11] european telecommunications standards institute, etsi en 300 324, "european telecommunication standard, v interfaces at the digital local exchange (le); v5.1 interface for the support of access network (an)", april 2000 [12] european telecommunications standards institute, etsi en 300 347, "european telecommunication standard, v interfaces at the digital local exchange (le); v5.2 interface for the support of access network (an)", december 1999 [13] european telecommunications standards institute, tbr 12, "technical basis for regulation, business telecommunications (btc); open network provision (onp) technical requirements; 2 048 kbit/s digital unstructured leased line (d2048u); attachment requirements for terminal equipment", edition 1, december 1993; amendment 1 to edition 1 - january 1996 [14] european telecommunications standards institute, tbr 13, "technical basis for regulation, business telecommunications (btc); 2048 kbit/s digital structured leased lines (d2048s); attachment requirements for terminal equipment interface", edition 1 - january 1996 [15] enterprise computer telephony forum (ectf) hardware compatibility specification: ct bus, h.100 revision 1.0, april 1997 [16] federal communications commission, fcc part 68 [17] institute of electrical and electronics engineers inc. (ieee), ieee std 1149.1-2001, "ieee standard test access port and boundary-scan architecture", june 2001 [18] international telecommunication union (itu), itu-t g.703, ?physical/electrical characteristics of hierarchical digital interfaces?, november 2001 [19] international telecommunication union (itu), itu-t g.704, ?synchronous frame structures used at 1544, 6312, 2048, 8448 and 44736 kbit/s hierarchical levels?, december 1998 [20] international telecommunication union (itu), itu-t g.705, ?characteristics of plesiochronous digital hierarchy (pdh) equipment functional blocks ?, october 2000 falc ? 56 pef 2256 h/e user?s manual 511 ds1.1, 2003-10-23 hardware description [21] international telecommunication union (itu), itu-t g.706, ?frame alignment and cycl ic redundancy check (crc) procedures relating to basic frame structures defined in recommendation g.704?, april 1991 [22] international telecommunication union (itu), itu-t g.732, ?characteristics of primary pcm multiplex equipment operating at 2048 kbit/s?, november 1988 [23] international telecommunication union (itu), itu-t g.733, ?characteristics of primary pcm multiplex equipment operating at 1544 kbit/s?, november 1988 [24] international telecommunication union (itu), itu-t g.735, ?characteristics of primary pcm multiplex equipment operating at 2048 kbit/s and offering synchronous digital access at 384 kbit/s and/or 64 kbit/s?, november 1988 [25] international telecommunication union (itu), itu-t g.736, ?characteristics of a synchronous digital multiplex equipment operating at 2048 kbit/s?, march 1993 [26] international telecommunication union (itu), itu-t g.737, ?characteristics of an external access equipment oprating at 2048 kbit/s offering synchronous digital access at 384 kbit/s and/or 64 kbit/s?, november 1988 [27] international telecommunication union (itu), itu-t g.738, ?characteristics of primary pcm multiplex equipment operating at 2048 kbit/s and offering synchronous digital access at 320 kbit/s and/or 64 kbit/s?, november 1988 [28] international telecommunication union (itu), itu-t g.739, ?characteristics of an external access equipment operating at 2048 kbit/s and offering synchronous digital access at 320 kbit/s and/or 64 kbit/s?, november 1988 [29] international telecommunication union (itu), itu-t g.823, ?the control of jitter and wander within digital networks which are based on the 2048 kbit/s hierarchy ?, march 2000 [30] international telecommunication union (itu), itu-t g.824, ?the control of jitter and wander within digital networks which are based on the 1544 kbit/s hierarchy ?, march 2000 [31] international telecommunication union (itu), itu-t g.962, ?access digital section for isdn primary rate at 2048 kbit/s ?, march 1993 falc ? 56 pef 2256 h/e user?s manual 512 ds1.1, 2003-10-23 hardware description [32] international telecommunication union (itu), itu-t g.963, ?access digital section for isdn primary rate at 1544 kbit/s ?, march 1993 [33] international telecommunication union (itu), itu-t g.964, ?v-interfaces at the digital local exchange (le) - v5.1 interface (based on 2048 kbit/s) for the support of access network (an)?, march 2001 [34] international telecommunication union (itu), itu-t i.431, ?primary rate user-network interface - layer 1 specification?, march 1993 and amendment 1 of june 1997 [35] international telecommunication union (itu), itu-t q.703, ?signalling link ?, july 1996 [36] jedec solid state products engineering council, jedec design standard - ?design requirements for outlines of solid state and related products - jedec standard no. 95-1, section 14 - ball grid array package?, revision c, june 2000 [37] telcordia technologies, gr-253-core, "synchronous optical network (sonet) transport systems: common generic criteria", issue 3, september 2000 [38] telcordia technologies, gr-499-core, "transport systems generic requirements (tsgr): common requirements", issue 2, december 1998 [39] telcordia technologies, gr-1089-core, "electromagnetic compatibility and electrical safety - generic criteria for network telecommunications equipment", issue 2, december 1997; revision 1, february 1999 [40] the global organization for multi-vendor integration protocol (go-mvip) h-mvip standard, release 1.1a [41] the telecommunication technology commitee (ttc), jt-g.703, ?physical/electrical characteristics of hierarchical digital interfaces? [42] the telecommunication technology commitee (ttc), jt-g.704, ?synchronous frame structures used at 1544, 6312, 2048, 8448 and 44736 kbit/s hierarchical levels? [43] the telecommunication technology commitee (ttc), jt-g.706, "frame alignment and cyclic redundancy check (crc) procedures relating to basic frame structures defined in recommendation g.704" falc ? 56 pef 2256 h/e user?s manual 513 ds1.1, 2003-10-23 hardware description [44] the telecommunication technology commitee (ttc), jt-g.733, ?characteristics of primary pcm multiplex equipment operating at 1544 kbit/s? [45] the telecommunication technology commitee (ttc), jt-i.431, ?primary rate user-network interface - layer 1 specification? user?s manual 514 ds1.1, 2003-10-23 hardware description falc ? 56 pef 2256 h/e a alarm simulation 121, 193 application notes 501 applications 21, 22 b bec 437 bit oriented message 219 bit oriented messages 141 bit robbing 141, 168, 169 boundary scan 56, 470, 501 bsn 103, 168 c cas 80, 81, 104, 141, 168, 169, 201 ccbx 379 ccr1 232, 353 ccr2 234, 356 ccr3 285, 410 ccr4 287, 412 ccr5 288, 413 cec 435 cec1 313 cec2 315 cec3 316 channel associated signaling 80, 81, 104 channel translation mode 135 clear channel 158, 160, 168, 169 clock and data recovery 64, 123 clocking unit 59, 63 cmdr 227, 348 cmdr2 283, 408 cmdr3 283, 408 cmdr4 284, 409 cmr1 269, 395 cmr2 270, 396 cmr3 274, 400 coec 438 crc16 78, 103, 139, 168 crc-multiframe 86 cvc 312, 434 d d4 142, 147 data link access 221 dec 274, 400 defect insertion 121, 193 doubleframe format 83 e ebc 313, 314, 436 elastic buffer 74, 100, 133, 163 error counter 95, 157 esf 142, 148, 169 esm 274, 400 f f12 142, 143 f24 142, 148, 169 f4 142, 146 f72 142, 143, 221 fec 311, 433 fifo structure 52 fisu 78, 103, 139, 168 fmr0 238, 360 fmr1 240, 362 fmr2 242, 364 fmr3 255 fmr4 368 fmr5 370 fractional e1 access 268 fractional t1/j1 access 394 frame aligner 19 frs0 304, 428 frs1 307, 430 frs2 432 fsn 103, 168 g gcm1 291, 416 gcm2 291, 416 index user?s manual 515 ds1.1, 2003-10-23 hardware description falc ? 56 pef 2256 h/e gcm3 291, 416 gcm4 291, 416 gcm5 292, 417 gcm6 292, 417 gcm7 292, 417 gcm8 292, 417 gcr 273, 399 gis 54, 335, 455 glc1 298, 423 gpc1 281, 406 h hdlc 200, 211 i ibis model 502 icbx 256, 380 idle 253, 378 ieee 1149.1 56 ierr 237, 360 imrx 237, 359 in-band loop 96, 158 initialization in e1 mode 195 initialization in t1/j1 mode 203 int 54 interrupt interface 54 ipc 55, 231, 352 is 54 isr0 323, 445 isr1 325, 447 isr2 327, 448 isr3 329, 450 isr4 330, 451 isr5 332, 453 j j1-features 193 jitter 70, 99, 129, 161 l lcr1 262, 387 lcr2 264, 389 lcr3 264, 389 lim0 257, 380 lim1 258, 383 lim2 261, 386 line build-out 165 line coding 65, 124 line interface 18, 477 line monitoring 66, 126 local loop 119, 191 loop 243, 367 loss of signal 69, 128 lssu 78, 139 m master clock 59 mfpi 343, 463 microprocessor interface 20, 51, 471 mode 229, 350 mode2 289, 414 mode3 290, 415 msu 78, 139 o one-second timer 95, 157 p payload loop back 120, 190 p-bga-81 500 pc1...4 277, 402 pc5 279, 405 pc6 282, 407 pcd 260, 384 pcr 260, 385 performance monitoring 88, 155 periodical performance report 169 ppr 169, 408, 414 protection 501 protection switching 127 pseudo-random bit sequence 117, 188 pulse density 159 user?s manual 516 ds1.1, 2003-10-23 hardware description falc ? 56 pef 2256 h/e pulse shaper 101, 165 pulse template 492, 493, 494 r rah1 230, 351 rah2 230, 351 ral1 230, 351 ral2 231, 352 rbc2 337, 457 rbc3 337, 457 rbch 323, 444 rbcl 323, 444 rbd 302, 426 rc0 248, 373 rc1 249, 375 rdl1 439 rdl2 439 rdl3 440 receive equalization network 64, 123 receive line attenuation indication 64, 123 receive line interface 63, 122 register addresses 223, 299, 344, 424 remote loop 117, 188 res 303, 427 reset 195, 203 rfifo 301, 426 rfifo2 343, 463 rfifo3 343, 463 rs1...12 456 rs1...16 336 rsa6s 318 rsax 317 rsis 321, 442 rsis2 339, 458 rsis3 341, 461 rsp 309 rsp1 319, 440 rsp2 319, 440 rsw 308 rtr1...4 235 rtrx 357 s sa bit access 218 sapi 414 sf 147 sic1 265, 390 sic2 266, 391 sic3 267, 393 signaling controller 20, 77, 102, 138, 167 single channel loop back 120, 192 sis 320, 441 sis2 337, 457 sis3 340, 460 slc96 142, 151 software 501 ss7 78, 103, 139, 167, 229, 350 su 78, 103, 139, 168 system interface 105, 171, 480 t test access port 56 time-slot assigner 116, 187 tpc0 297, 422 transmit line interface 98, 160 transmit line monitor 101, 166 transparent mode 214 tsbs1 295, 420 tsbs2 295, 420 tsbs3 296, 421 tseo 294, 419 tss2 296, 421 tss3 297, 422 tswm 252 ttr1...4 236 ttrx 358 v vis 55 vstr 303, 427 user?s manual 517 ds1.1, 2003-10-23 hardware description falc ? 56 pef 2256 h/e x xc0 246, 371 xc1 247, 372 xdlx 378 xfifo 227, 348 xfifo2 293, 418 xfifo3 293, 418 xpmx 251, 377 xs1...12 401 xs1...16 276 xsax 254 xsp 245 xsw 244 xts16ra 232 www.infineon.com published by infineon technologies ag |
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